# US 2013/0159958 A1 · Equation based transient circuit optimization > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159958 A1 - Document ID: US20130159958A1 - Status: Published application - Kind: A1 - Application number: 13/716,067 - Filed: 2012-12-14 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: Synopsys, Inc. - Inventors: David Colleran; Talal Al-Attar; Sunderarajan Sunderesan Mohan - Web page: https://patentgrep.com/patent/US20130159958A1 ## CPC - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Circuit simulation can be performed on digital, analog, and mixed signal types of circuitry. Phases of operation are identified for a circuit and transient behavior is analyzed. Multiple time points are identified and the circuit is replicated for those time points with evaluation of the circuitry performed at those various time points. Simultaneous optimization is performed across the time points. Transistors and other devices can have their lengths, widths, and number of fingers optimized. Simulation can include determining Kirchhoff current law equations for various nodes within the circuit. Equations describing device operation can include non-convex signomial equations and convex polynomial equations. ## Claims ### Claim 1 A computer-implemented method for circuit evaluation comprising: obtaining a representation for a circuit wherein the representation describes a plurality of devices and connections between the devices; importing models for the plurality of devices included in the representation; identifying N time points of operation for the circuit; instantiating the circuit N times; and optimizing the circuit simultaneously at the N time points. ### Claim 2 (depends on 1) The method of claim 1 wherein the devices include one or more of transistors, capacitors, inductors, or resistors. ### Claim 3 (depends on 1) The method of claim 1 wherein the optimizing includes setting transistor dimensions within the circuit. ### Claim 4 (depends on 3) The method of claim 3 wherein the transistor dimensions includes one or more of lengths, widths, or finger numbers. ### Claim 5 (depends on 1) The method of claim 1 wherein the optimizing includes one or more of reducing delay through the circuit, reducing power consumption for the circuit, or reducing area for the circuit. ### Claim 6 (depends on 1) The method of claim 1 further comprising capturing transient behavior of the circuit for each of the N time points. ### Claim 7 (depends on 1) The method of claim 1 wherein transistors, within the circuit, transition through a plurality of regions of operation. ### Claim 8 (depends on 7) The method of claim 7 wherein simulation is performed on the plurality of regions of operation. ### Claim 9 (depends on 7) The method of claim 7 further comprising linking each of the plurality of regions for circuit design. ### Claim 10 (depends on 7) The method of claim 7 wherein the regions of operation include two or more of off, sub-threshold leakage, linear, and saturated states. ### Claim 11 (depends on 1) The method of claim 1 wherein the representation includes a schematic. ### Claim 12 (depends on 1) The method of claim 1 wherein the representation includes a netlist. ### Claim 13 (depends on 1) The method of claim 1 wherein the time points are linked by a voltage delta. ### Claim 14 (depends on 13) The method of claim 13 wherein the voltage delta is based on dynamic currents within the circuit. ### Claim 15 (depends on 14) The method of claim 14 wherein the dynamic currents are based on capacitances within the circuit. ### Claim 16 (depends on 1) The method of claim 1 wherein the time points are linked by a current delta. ### Claim 17 (depends on 16) The method of claim 16 wherein the current delta is based on dynamic voltages within the circuit. ### Claim 18 (depends on 17) The method of claim 17 wherein the dynamic voltages are based on inductances within the circuit. ### Claim 19 (depends on 1) The method of claim 1 further comprising determining DC currents for nodes within the circuit. ### Claim 20 (depends on 19) The method of claim 19 further comprising generating Kirchhoff current law equations for the nodes using the DC currents. ### Claim 21 (depends on 19) The method of claim 19 further comprising determining dynamic currents for the nodes within the circuit. ### Claim 22 (depends on 21) The method of claim 21 further comprising generating Kirchhoff current law equations for the nodes using the dynamic currents. ### Claim 23 (depends on 22) The method of claim 22 wherein the Kirchhoff current law equations are relaxed at an initial solver iteration. ### Claim 24 (depends on 1) The method of claim 1 wherein the models for the plurality of devices include convex polynomial equations. ### Claim 25 (depends on 1) The method of claim 1 wherein the models for the plurality of devices include non-convex signomial equations. ### Claim 26 (depends on 1) The method of claim 1 wherein the optimizing includes non-linear optimization techniques. ### Claim 27 (depends on 1) The method of claim 1 further comprising determining a DC operating point for the circuit. ### Claim 28 (depends on 27) The method of claim 27 further comprising initializing the plurality of devices based on the DC operating point. ### Claim 29 (depends on 1) The method of claim 1 further comprising constraining behavior of the circuit during the N times. ### Claim 30 (depends on 1) The method of claim 1 further comprising generating transient equations for the circuit. ### Claim 31 (depends on 1) The method of claim 1 further comprising generating AC noise equations for the circuit. ### Claim 32 (depends on 1) The method of claim 1 further comprising optimizing a second circuit coupled to the circuit wherein the circuit and the second circuit are optimized together. ### Claim 33 (depends on 32) The method of claim 32 wherein the circuit and the second circuit are optimized at different time points. ### Claim 34 (depends on 1) The method of claim 1 wherein the circuit includes multiple levels of hierarchy. ### Claim 35 (depends on 34) The method of claim 34 wherein the multiple levels of hierarchy are optimized together. ### Claim 36 A computer program product embodied in a non-transitory computer readable medium for circuit evaluation, the computer program product comprising: code for obtaining a representation for a circuit wherein the representation describes a plurality of devices and connections between the devices; code for importing models for the plurality of devices included in the representation; code for identifying N time points of operation for the circuit; code for instantiating the circuit N times; and code for optimizing the circuit simultaneously at the N time points. ### Claim 37 A computer system for circuit evaluation comprising: a memory which stores instructions; one or more processors coupled to the memory wherein the one or more processors are configured to: obtain a representation for a circuit wherein the representation describes a plurality of devices and connections between the devices; import models for the plurality of devices included in the representation; identify N time points of operation for the circuit; instantiate the circuit N times; and optimize the circuit simultaneously at the N time points.