# US 2013/0159953 A1 · Performing statistical timing analysis with non-separable statistical and deterministic variations

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- Number: US 2013/0159953 A1
- Document ID: US20130159953A1
- Status: Published application
- Kind: A1
- Application number: 13/768,563
- Filed: 2013-02-15
- Published: 2013-06-20
- Earliest claimed: 2010-11-10
- Assignees: International Business Machines Corporation
- Inventors: Jeffrey G. Hemmett; Debjit Sinha; Natesan Venkateswaran; Chandramouli Visweswariah; Vladimir Zolotov
- Web page: https://patentgrep.com/patent/US20130159953A1

## CPC

- G06F 30/3323: using formal methods, e.g. equivalence checking or property checking
- G06F 2111/08: Probabilistic or stochastic CAD
- G06F 2119/12: Timing analysis or timing optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and slews at the corresponding corner.

## Claims

### Claim 1

A method for performing timing analysis of an integrated circuit chip, the method comprising:
computing a timing quantity of the integrated circuit chip, wherein the timing quantity depends on at least a first process parameter that is deterministic and corner-based and a second process parameter that is non-separable with the first process parameter; and
performing a single timing run using the timing quantity, wherein the single timing run produces an arrival time, a required arrival time, or a timing slack at a node of the integrated circuit chip.

### Claim 2 (depends on 1)

The method of claim 1, wherein the timing quantity is a delay or a signal slew of a gate or wire in the integrated circuit chip.

### Claim 3 (depends on 1)

The method of claim 1, wherein the timing quantity is an arrival time at the input of the integrated circuit chip or a required arrival time at an output of the integrated circuit chip.

### Claim 4 (depends on 1)

The method of claim 1 wherein the computing comprises:
extending a linear canonical form of the timing quantity to account for an interaction of the first process parameter with the second process parameter; and
projecting a value for the first process parameter to a corner associated with the first process parameter; and
calculating the timing quantity in accordance with the linear canonical form, after the projecting.

### Claim 5 (depends on 4)

The method of claim 4, wherein the extending comprises:
modeling a linear portion of a variation of the first processing parameter; and
modeling the interaction of the first process parameter with the second process parameter as a cross-product.

### Claim 6 (depends on 4)

The method of claim 4, wherein the projecting comprises:
substituting a value associated with the corner for the first process parameter in the linear canonical form that is extended.

### Claim 7 (depends on 4)

The method of claim 4, wherein the projecting comprises:
substituting a value associated with a first corner for the first process parameter in a first version the linear canonical form that is extended, wherein the first corner is associated with a lowest value for the first process parameter; and
substituting a value associated with a second corner for the first process parameter in a second version the linear canonical form that is extended, wherein the second corner is associated with a highest value for the first process parameter.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
performing linear interpolation between the first version the linear canonical form that is extended and the second version the linear canonical form that is extended.

### Claim 9 (depends on 5)

The method of claim 5, wherein the calculating comprises:
computing a sensitivity to the cross-product using finite differencing.

### Claim 10 (depends on 9)

The method of claim 9, wherein the finite differencing is performed for each process corner that involves a variation of the first process parameter and the second process parameter simultaneously.

### Claim 11 (depends on 9)

The method of claim 9, wherein the computing the sensitivity comprises:
modeling the interaction of the first process parameter with the second process parameter as a quadratic or higher-order term, where the first process parameter is non-linear; and
computing a sensitivity to the quadratic or higher-order term in accordance with a middle range corner for the first process parameter.

### Claim 12 (depends on 5)

The method of claim 5, wherein the calculating comprises:
assigning the sensitivity assuming a known percentage of variability.

### Claim 13 (depends on 4)

The method of claim 4, wherein the method further comprises:
modeling the integrated circuit chip as a timing graph, wherein each node in the timing graph represents an input or an output of a gate in the integrated circuit chip and each edge in the timing graph represents a propagation of a signal in the integrated circuit chip.

### Claim 14 (depends on 13)

The method of claim 13, wherein the performing comprises:
propagating the timing quantity through the timing graph; and
computing an arrival time at the node of the integrated circuit chip, in accordance with the timing quantity as propagated.

### Claim 15 (depends on 14)

The method of claim 14, wherein the propagating comprises:
adding the linear canonical form of the timing quantity, as extended, and an extended linear canonical form of at least one more timing quantity.

### Claim 16 (depends on 15)

The method of claim 15, wherein the adding comprises:
summing all sensitivities and cross-products in the linear canonical form of the timing quantity, as extended, and the extended linear canonical form of the at least one more timing quantity.

### Claim 17 (depends on 14)

The method of claim 14, wherein the arrival time is a statistical minimum or a statistical maximum among all arrival times at the node of the integrated circuit chip.

### Claim 18 (depends on 14)

The method of claim 14, wherein the computing comprises:
projecting an arrival time on an input edge of the node of the integrated circuit chip at each corner associated with the first process parameter, to produce a plurality of quantities;
computing a statistical maximum or a statistical minimum among the plurality of quantities at each corner associated with the first process parameter, to produce a simple canonical form at each corner associated with the first process parameter; and
combining the simple canonical form for each corner associated with the first process parameter to produce an extended canonical form.

### Claim 19 (depends on 1)

The method of claim 1, wherein the arrival time is used in a circuit optimization process.

### Claim 20 (depends on 1)

The method of claim 1, wherein the arrival time is used in a sign-off timing process.

### Claim 21 (depends on 1)

The method of claim 1, wherein the arrival time is used in a selective voltage binning process.

### Claim 22 (depends on 1)

The method of claim 1, wherein the first process parameter is supply voltage.

### Claim 23 (depends on 1)

The method of claim 1, wherein the first process parameter is temperature.

### Claim 24

A computer readable storage medium containing an executable program for performing timing analysis of an integrated circuit chip, where the program performs steps of:
computing a timing quantity of the integrated circuit chip, wherein the timing quantity depends on at least a first process parameter that is deterministic and corner-based and a second process parameter that is non-separable with the first process parameter; and
performing a single timing run using the timing quantity, wherein the single timing run produces an arrival time, a required arrival time, or a timing slack at a node of the integrated circuit chip.

### Claim 25

Apparatus for performing timing analysis of an integrated circuit chip, the apparatus comprising:
means for computing a timing quantity of the integrated circuit chip, wherein the timing quantity depends on at least a first process parameter that is deterministic and corner-based and a second process parameter that is non-separable with the first process parameter; and
means for performing a single timing run using the timing quantity, wherein the single timing run produces an arrival time, a required arrival time, or a timing slack at a node of the integrated circuit chip.