# US 2013/0159952 A1 · Combining multiple timing modes of integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159952 A1 - Document ID: US20130159952A1 - Status: Published application - Kind: A1 - Application number: 13/716,501 - Filed: 2012-12-17 - Published: 2013-06-20 - Earliest claimed: 2011-12-20 - Assignees: International Business Machines Corporation - Inventors: Jia Niu; Hong Wei Dai; Tie Peng Cheng; Gong Qiong Li; Xia Li; Fan Zhou - Web page: https://patentgrep.com/patent/US20130159952A1 ## CPC - G06F 30/3315: using static timing analysis [STA] - G06F 30/3323: using formal methods, e.g. equivalence checking or property checking - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F 30/396: Clock trees - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method and system for combining multiple timing modes of an integrated circuit. The method includes the steps of: creating logic groups for at least one logic device in the circuit according to at least one clock driving the at least one logic device, performing static timing analysis to the circuit in multiple given timing modes, obtaining at least one relationship between the logic groups in each of the multiple given timing modes according to a result of the static timing analysis, and combining the obtained at least one relationship between the logic groups in each of the multiple given timing modes ## Claims ### Claim 1 A method of combining multiple timing modes of an integrated circuit, the method comprising the steps of: creating logic groups for at least one logic device in the circuit according to at least one clock driving the at least one logic device; performing static timing analysis to the circuit in multiple given timing modes; obtaining at least one relationship between the logic groups in each of the multiple given timing modes according to a result of the static timing analysis; and combining the obtained at least one relationship between the logic groups in each of the multiple given timing modes. ### Claim 2 (depends on 1) The method according to claim 1, wherein logic devices driven by a same clock are in a same group among the logic groups created. ### Claim 3 (depends on 2) The method according to claim 2, wherein the at least one relationship between the logic groups in the each timing mode comprise: i) whether there exists an interaction between the logic groups, ii) an interaction direction associated with the logic groups, iii) an interaction parameter associated with the logic groups, and iv) a parameter of internal interaction associated with at least one of the logic groups. ### Claim 4 (depends on 3) The method according to claim 3, wherein to determine whether an interaction exists between the logic groups and to obtain an interaction direction is achieved by one of the following: i) propagating the at least one clock in the circuit during the static timing analysis to determine whether the interaction exists and to obtain the interaction direction, ii) forward tracing respective logic devices in at least one of the logic groups to determine whether the interaction exists and to obtain the interaction direction, iii) backward tracing respective logic devices in at least one of the logic groups to determine whether the interaction exists and to obtain the interaction direction, iv) traversing all connection relationships between all logic devices in the circuit to determine whether the interaction exists and to obtain the interaction direction. ### Claim 5 (depends on 3) The method according to claim 3, wherein the interaction parameter associated with the logic groups is obtained by a circuit that contains timing information and that is outputted during the static timing analysis. ### Claim 6 (depends on 3) The method according to of claims 3, wherein the interaction parameter associated with the logic groups comprises a delay and timing adjustment DTA parameter, and the parameter of internal interaction of the at least one logic group further comprises a minimum pulse width parameter of the clock. ### Claim 7 (depends on 6) The method according to claim 6, wherein the combining step further comprises the steps of: for any two logic groups, obtaining a minimum DTA parameter according to DTA parameters between the two logic groups in each of the multiple timing modes; and in the at least one logic group associated with the parameter of internal interaction, obtaining a maximum one of minimum pulse width parameters of the clock according to minimum pulse width parameters of the clock in timing modes corresponding to the obtained minimum DTA parameter. ### Claim 8 (depends on 1) The method according to claim 1, further comprising the step of: generating a timing constraint file from a result of the combination. ### Claim 9 A system for combining multiple timing modes of an integrated circuit, the system comprising: grouping means configured to create logic groups for at least one logic device in the circuit according to at least one clock driving the at least one logic device; static timing analysis means configured to perform static timing analysis to the circuit in multiple given timing modes; relationship obtaining means configured to obtain at least one relationship between the logic groups in each of the multiple given timing modes according to a result of the static timing analysis; and combining means configured to combine the obtained at least one relationship between the logic groups in each of the multiple given timing modes. ### Claim 10 (depends on 9) The system according to claim 9, wherein logic devices driven by a same clock are in a same logic group of the logic groups created. ### Claim 11 (depends on 10) The system according to claim 10, wherein the at least one relationship between the logic groups in the each timing mode comprise: i) whether there exists an interaction between the logic groups, ii) an interaction direction associated with the logic groups, iii) an interaction parameter associated with the logic groups, and iv) a parameter of internal interaction associated with at least one of the logic groups. ### Claim 12 (depends on 11) The system according to claim 11, wherein the interaction parameter associated with the logic groups is obtained by a circuit that contains timing information and that is outputted during the static timing analysis. ### Claim 13 (depends on 11) The system according to any of claim 11, wherein the interaction parameter associated with the logic groups comprises a delay and timing adjustment DTA parameter, and the parameter of internal interaction of the at least one logic group further comprises a minimum pulse width parameter of the clock. ### Claim 14 (depends on 15) The system according to claim 15, wherein the combining means is further configured to: for any two logic groups, obtaining a minimum DTA parameter according to DTA parameters between the two logic groups in each of the multiple timing modes; and in the at least one logic group associated with the parameter of internal interaction, obtaining a maximum one of minimum pulse width parameters of the clock according to minimum pulse width parameters of the clock in timing modes corresponding to the obtained minimum DTA parameter. ### Claim 15 (depends on 9) The system according to claim 9, further comprising generating means configured to generate a timing constraint file from a result of the combination.