# US 2013/0159947 A1 · Guiding design actions for complex failure modes

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- Number: US 2013/0159947 A1
- Document ID: US20130159947A1
- Status: Published application
- Kind: A1
- Application number: 13/460,369
- Filed: 2012-04-30
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: International Business Machines Corporation
- Inventors: ANNE ELIZABETH GATTIKER; Sani Richard Nassif
- Web page: https://patentgrep.com/patent/US20130159947A1

## CPC

- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 2111/08: Probabilistic or stochastic CAD
- G06F 2117/02: Fault tolerance, e.g. for transient fault suppression
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for guiding design actions for complex failure modes in an integrated circuit (IC) design is provided in the illustrative embodiments. A probability of failure estimate of a circuit according to the IC design is received, the probability being determined using a simulation. A sensitivity of the probability of failure to a variable associated with a component in the circuit is calculated, wherein the sensitivity is determined by an estimation without the simulation. The sensitivity is depicted relative to the component in the IC design such that the sensitivity is associated with the component and a visual relationship between the component and the sensitivity is usable for adjusting a characteristic of the component to reduce the probability of failure of the circuit.

## Claims

### Claim 1

A method for guiding design actions for complex failure modes in an integrated circuit (IC) design, the method comprising:
receiving a probability of failure estimate of a circuit according to the IC design, the probability being determined using a simulation;
computing, in an application executing using a processor, a sensitivity of the probability of failure to a variable associated with a component in the circuit, wherein the sensitivity is determined by performing an estimation without performing the simulation; and
depicting the sensitivity relative to the component in the IC design such that the sensitivity is associated with the component and a visual relationship between the component and the sensitivity of the probability of failure to the variable associated with the component is usable for adjusting a characteristic of the component to reduce the probability of failure of the circuit.

### Claim 2 (depends on 1)

The method of claim 1, wherein the variable is one of a set of variables associated with the component, wherein the variable is assigned different values in the simulation, and wherein the sensitivity corresponds to a change in the probability of failure responsive to a change in a value of the variable associated with the component.

### Claim 3 (depends on 1)

The method of claim 1, wherein the variable is a feature of the component.

### Claim 4 (depends on 1)

The method of claim 1, wherein the variable is an operating condition of the component.

### Claim 5 (depends on 1)

The method of claim 1, wherein the depicting further comprises: plotting a plurality of probabilities of failure, wherein a difference between two probabilities of failure in the plurality of probabilities of failure corresponds to the sensitivity.

### Claim 6 (depends on 1)

The method of claim 1, wherein the component is a plurality of replicas of the component, wherein the variable corresponds to a designable parameter of the plurality of replicas of the component, and wherein the sensitivity enables adjusting the characteristic associated with each replica of the component.

### Claim 7 (depends on 1)

The method of claim 1, wherein the circuit corresponds to a portion of the IC design.