# US 2013/0159813 A1 · Memory controller ecc

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- Number: US 2013/0159813 A1
- Document ID: US20130159813A1
- Status: Published application
- Kind: A1
- Application number: 13/768,203
- Filed: 2013-02-15
- Published: 2013-06-20
- Earliest claimed: 2006-03-20
- Assignees: Micron Technology, Inc.
- Inventors: William H. RADKE
- Web page: https://patentgrep.com/patent/US20130159813A1

## CPC

- H03M 13/05: using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Memory controllers having a data buffer coupled to receive and hold data from a memory device, and an Error Correction Code (ECC) generator/checker coupled to the data buffer. The ECC generator/checker is configured to generate ECC codes for the data and to compare the generated ECC codes with ECC codes received with the data. The memory controllers are configured to permit different ECC coverage area sizes and/or different ECC code types for different portions of the memory device.

## Claims

### Claim 1

A memory controller, comprising
a data buffer coupled to receive and hold data from a memory device;
an Error Correction Code (ECC) generator/checker coupled to the data buffer, wherein the ECC generator/checker is configured to generate ECC codes for the data and to compare the generated ECC codes with ECC codes received with the data;
wherein the ECC generator/checker is configured to generate ECC codes using a particular ECC coverage area size for data received from a particular portion of the memory device; and
wherein the memory controller is configured to modify the particular ECC coverage area size for the particular portion of the memory device.

### Claim 2 (depends on 1)

The memory controller of claim 1, wherein the particular ECC coverage area size and the modified particular ECC coverage area size each comprise an integer number of sectors of user data.

### Claim 3 (depends on 1)

The memory controller of claim 1, wherein the memory controller is further configured to modify the particular ECC coverage area size for the particular portion of the memory device in response to a use characteristic of the memory device.

### Claim 4 (depends on 1)

The memory controller of claim 1, wherein the memory controller is further configured to modify the particular ECC coverage area size for the particular portion of the memory device based on a data type stored in the particular portion of the memory device.

### Claim 5 (depends on 1)

The memory controller of claim 1, wherein the memory controller is further configured to modify the particular ECC coverage area size for the particular portion of the memory device based on a bit error rate of the particular portion of the memory device.

### Claim 6 (depends on 1)

The memory controller of claim 1, wherein the memory controller is further configured to modify an ECC code type for the particular portion of the memory device when modifying the particular ECC coverage area size for the particular portion of the memory device.

### Claim 7 (depends on 6)

The memory controller of claim 6, wherein the modified ECC code type for the particular portion of the memory device is an ECC code type having a different math base than an ECC code type for the particular portion of the memory device before modification.

### Claim 8 (depends on 6)

The memory controller of claim 6, wherein the memory controller is further configured to use a different ECC code type for a different portion of the memory device.

### Claim 9 (depends on 1)

The memory controller of claim 1, wherein the memory controller is further configured to use a different ECC coverage area size for a different portion of the memory device.

### Claim 10 (depends on 1)

The memory controller of claim 1, wherein the memory controller is further configured to perform a read operation on the particular portion of the memory device, to store user data read from the particular portion of the memory device to the data buffer, and to verify the user data by comparing the generated ECC codes to ECC codes read from the particular portion of the memory device.

### Claim 11

A memory controller, comprising
a data buffer coupled to receive and hold data from a memory device;
an Error Correction Code (ECC) generator/checker coupled to the data buffer, wherein the ECC generator/checker is configured to generate ECC codes for the data and to compare the generated ECC codes with ECC codes received with the data;
wherein the ECC generator/checker is configured to use a first ECC code type for data received from a first portion of the memory device and to use a second ECC code type for data received from a second portion of the memory device.

### Claim 12 (depends on 11)

The memory controller of claim 11, wherein the first ECC code type has a different math base than the second ECC code type.

### Claim 13 (depends on 11)

The memory controller of claim 11, wherein the first ECC code type is associated with a first ECC coverage area size and the second ECC code type is associated with a second ECC coverage area size.

### Claim 14 (depends on 13)

The memory controller of claim 13, wherein the first ECC coverage area size and the second ECC coverage area size each comprise an integer number of sectors of user data.

### Claim 15 (depends on 11)

The memory controller of claim 11, wherein the memory controller is configured to modify the first ECC code type based on at least one criteria selected from the group consisting of a data type stored in the first portion of the memory device and a bit error rate of the first portion of the memory device.

### Claim 16 (depends on 11)

The memory controller of claim 11, wherein the memory controller is further configured to perform a read operation on a particular portion of the memory device, to store user data read from the particular portion of the memory device to the data buffer, and to verify the user data by comparing the generated ECC codes for the user data read from the particular portion of the memory device to ECC codes read from the particular portion of the memory device.

### Claim 17

A memory controller, comprising
a data buffer coupled to receive and hold data from a memory device;
an Error Correction Code (ECC) generator/checker coupled to the data buffer, wherein the ECC generator/checker is configured to generate ECC codes for the data and to compare the generated ECC codes with ECC codes received with the data;
wherein the ECC generator/checker is configured to generate ECC codes using a first ECC coverage area size for data received from a first portion of the memory device and to generate ECC codes using a second ECC coverage area size for data received from a second portion of the memory device.

### Claim 18 (depends on 17)

The memory controller of claim 17, wherein the first ECC coverage area size is associated with a first ECC code type and the second ECC coverage area size is associated with a second ECC code type.

### Claim 19 (depends on 17)

The memory controller of claim 17, wherein the first ECC coverage area size and the second ECC coverage area size each comprise an integer number of sectors of user data.

### Claim 20 (depends on 17)

The memory controller of claim 17, wherein the memory controller is configured to modify the first ECC coverage area size based on at least one criteria selected from the group consisting of a data type stored in the first portion of the memory device and a bit error rate of the first portion of the memory device.