# US 2013/0159802 A1 · Testing of multi-clock domains

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- Number: US 2013/0159802 A1
- Document ID: US20130159802A1
- Status: Published application
- Kind: A1
- Application number: 13/739,799
- Filed: 2013-01-11
- Published: 2013-06-20
- Earliest claimed: 2010-04-23
- Assignees: STMicroelectronics International N.V.
- Inventors: Swapnil BAHL; Akhil GARG
- Web page: https://patentgrep.com/patent/US20130159802A1

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318594: {Timing aspects (clock circuits G01R31/318552)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.

## Claims

### Claim 1

A method for testing an integrated circuit (IC), the method comprising:
providing, based on a scan enable signal, capture pulses at a frequency of a first fast clock to a first clock domain of the IC;
delaying the scan enable signal by at least a time duration of the capture pulses at the frequency of the first fast clock; and
providing, based on the delaying, capture pulses at a frequency of a second fast clock to a second clock domain of the IC.

### Claim 2 (depends on 1)

The method as claimed in claim 1, further comprising providing a plurality of shift pulses to shift in a test pattern for testing the first clock domain and the second clock domain.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein the providing of shift pulses is performed at a frequency of a slow clock.

### Claim 4 (depends on 1)

The method as claimed in claim 1, further comprising masking cross-clock domain paths in the IC.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein the delaying comprises generating a delayed scan enable signal based on testing the first clock domain.