# US 2013/0159801 A1 · Adapting scan architectures for low power operation

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- Number: US 2013/0159801 A1
- Document ID: US20130159801A1
- Status: Published application
- Kind: A1
- Application number: 13/757,305
- Filed: 2013-02-01
- Published: 2013-06-20
- Earliest claimed: 2000-03-09
- Assignees: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US20130159801A1

## CPC

- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R 31/31721: {Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575)}
- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318575: {Power distribution; Power saving}
- G01R 31/318577: {AC testing, e.g. current testing, burn-in}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

## Claims

### Claim 1

An integrated circuit comprising:
A. logic circuitry including primary inputs, primary outputs, stimulus leads, and response leads;
B. scan path circuitry including a scan data input lead, a scan data output lead, and scan cells, each scan cell including:
i. multiplexer circuitry having a response input connected with one response lead, a scan data input, a scan enable input, and an output; and
ii. flip-flop circuitry having an input connected with the output of the multiplexer circuitry, a clock input, and a data output coupled with one stimulus bus lead;
C. a first scan path of serially connected scan cells that is selectably divided into a first part of scan cells and a second part of scan cells, the scan data input of the first scan cell in each part being connected to the scan data input lead, and each part including an output buffer having a data input coupled with the data output of the last scan cell in the part, a buffer enable input, and a data output coupled with the scan data output lead;
D. a second scan path of serially connected scan cells that is selectably divided into a first part of scan cells and a second part of scan cells, the scan data input of the first scan cell in each part being connected to the scan data input lead, and each part including an output buffer having a data input coupled with the data output of the last scan cell in the part, a buffer enable input, and a data output coupled with the scan data output lead;
E. adaptor circuitry having a first clock output lead connected with the clock inputs of the first part of scan cells in the first and second scan paths, and a second clock output lead connected with the clock inputs of the second part of scan cells in the first and second scan paths, the adaptor circuitry having a scan clock input and a scan enable input; and
F. a scan controller having a scan clock output connected to the scan clock input and a scan enable output connected to the scan enable input, the scan controller having tester inputs.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 in which the adaptor circuitry includes a scan enable output lead connected to the scan enable input of all the scan cells.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 in which the adaptor circuitry has a first buffer enable output lead connected with the buffer enable inputs of the first part of scan cells in the first and second scan paths, and a second buffer enable output lead connected with the buffer enable inputs of the second part of scan cells in the first and second scan paths.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 in which there are equal numbers of scan cells in each part.

### Claim 5 (depends on 1)

The circuit of claim 1 in which there are unequal numbers of scan cells in each part.