# US 2013/0159796 A1 · Read bias management to reduce read errors for phase change memory

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- Number: US 2013/0159796 A1
- Document ID: US20130159796A1
- Status: Published application
- Kind: A1
- Application number: 13/327,673
- Filed: 2011-12-15
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Micron Technology, Inc.
- Inventors: Ferdinando Bedeschi
- Web page: https://patentgrep.com/patent/US20130159796A1

## CPC

- G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/0038: {Power supply circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 29/021: {in voltage or current generators}
- G11C 29/026: {in sense amplifiers}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Subject matter disclosed herein relates to a memory device, and more particularly to read performance of phase change memory.

## Claims

### Claim 1

A method comprising:
applying a bias condition to read contents of a memory device;
counting read errors in said read contents of said memory device; and
modifying said bias condition in response to said count of errors exceeding a threshold number.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
determining coded data representing said read contents of said memory device by using an error correction code (ECC) engine.

### Claim 3 (depends on 2)

The method of claim 2, wherein said modifying said bias condition further comprises:
determining whether to modify said bias condition based, at least in part, on a comparison of a number of bits of said coded data in a first logic state to a number of bits of said coded data in a second logic state.

### Claim 4 (depends on 1)

The method of claim 1, wherein said bias condition comprises a read bias voltage.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
after modifying said bias condition, reading said contents of said memory device using said modified bias condition;
re-counting read errors resulting from said reading contents of said memory device; and
re-modifying said bias condition in response to said number of said read errors exceeding said threshold number.

### Claim 6 (depends on 2)

The method of claim 2, wherein said bias condition comprises a read bias voltage, and further comprising:
comparing a number of logic “0” bits of said coded data to a number of logic “1” bits of said coded data; and
decreasing said bias condition in response to said number of logic “0” bits exceeding said number of logic “1” bits and increasing said bias condition in response to said number of logic “1” bits exceeding said number of logic “0” bits.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
iteratively modifying said bias condition until said number of said read errors comprises a number less than or equal to said threshold number.

### Claim 8 (depends on 1)

The method of claim 1, wherein said memory device comprises a phase change memory (PCM).

### Claim 9 (depends on 2)

The method of claim 2, wherein said modifying said bias condition is performed in response to an ECC overflow event.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
sequentially stepping through multiple values of said bias condition; and
determining whether to continue said sequential stepping based, at least in part, on whether said number of said read errors comprises a number less than or equal to said threshold number.

### Claim 11

An apparatus comprising:
a controller to:
apply a bias condition to read contents of a memory device;
count read errors in said read contents of said memory device; and
modify said bias condition in response to said count of read errors exceeding a threshold number.

### Claim 12 (depends on 11)

The apparatus of claim 11, said controller to determine a codeword representing said read contents of said memory device by using an error correction code (ECC) engine.

### Claim 13 (depends on 12)

The apparatus of claim 12, said controller to:
determine whether to modify said bias condition based, at least in part, on a comparison of a number of bits of said codeword in a first logic state to a number of bits of said codeword in a second logic state.

### Claim 14 (depends on 12)

The apparatus of claim 12, wherein said bias condition comprises a read bias voltage, and wherein said controller is adapted to:
compare a number of logic “0” bits of said codeword to a number of logic “1” bits of said codeword; and
decrease said bias condition in response to said number of logic “0” bits exceeding said number of logic “1” bits and increase said bias condition in response to said number of logic “1” bits exceeding said number of logic “0” bits.

### Claim 15 (depends on 11)

The apparatus of claim 11, said controller to iteratively modify said bias condition until said number of said read errors comprises a number less than or equal to said threshold number.

### Claim 16 (depends on 11)

The apparatus of claim 11, wherein said memory device comprises a phase change memory (PCM).

### Claim 17

A system comprising:
a memory device comprising a phase change memory (PCM) array, said memory device further comprising a memory controller to:
apply a bias condition to read contents of said memory device;
count read errors in said read contents of said memory device; and
modify said bias condition in response to said count of read errors exceeding a threshold number; and
a processor to host one or more applications and to initiate reading said contents of said PCM array.

### Claim 18 (depends on 17)

The system of claim 17, said controller to:
determine a codeword representing said read contents of said memory device by using an error correction code (ECC) engine.

### Claim 19 (depends on 18)

The system of claim 18, said controller to:
determine whether to modify said bias condition based, at least in part, on a comparison of a number of bits of said codeword in a first logic state to a number of bits of said codeword in a second logic state.

### Claim 20

The system of claim. 18, said controller to:
iteratively modify said bias condition until said number of said read errors comprises a number less than or equal to said threshold number.