# US 2013/0159781 A1 · System For Compression Of Fixed Width Values In A Processor Hardware Trace

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0159781 A1
- Document ID: US20130159781A1
- Status: Published application
- Kind: A1
- Application number: 13/328,781
- Filed: 2011-12-16
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: MIPS Technologies, Inc.
- Inventors: James Hippisley Robinson
- Web page: https://patentgrep.com/patent/US20130159781A1

## CPC

- G06F 11/3636: {by tracing the execution of the program}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of tracing processor instructions includes forming a compressed trace stream with a dynamic unit width indicator and a value block. The dynamic unit width indicator includes an address/data width indicator qualified by a unit indicator. The unit value block has a width that is a function of the address/data width indicator and the unit indicator.

## Claims

### Claim 1

A method of tracing processor instructions, comprising:
invoking a trace stream mode; and
forming a compressed trace stream with a dynamic unit width indicator and a value block.

### Claim 2 (depends on 1)

The method of claim 1 wherein the dynamic unit width indicator includes an address/data width indicator qualified by a unit indicator.

### Claim 3 (depends on 2)

The method of claim 2 wherein the unit value block has a width that is a function of the address/data width indicator and the unit indicator.

### Claim 4 (depends on 2)

The method of claim 2 wherein the unit indicator is selected from a byte unit, a half word unit, a word unit and a double word unit.

### Claim 5

A computer readable storage medium storing executable instructions to characterize a circuit, comprising executable instructions to:
receive a fixed unit width trace stream; and
form a compressed trace stream with a dynamic unit width indicator and a unit value block.

### Claim 6 (depends on 5)

The computer readable storage medium of claim 5 wherein the dynamic unit width indicator includes an address/data width indicator and qualified by a fixed unit indicator.

### Claim 7 (depends on 6)

The computer readable storage medium of claim 6 wherein the value block has a width that is a function of the address/data width indicator and the unit indicator.

### Claim 8 (depends on 6)

The computer readable storage medium of claim 6 wherein the unit indicator is selected from a byte unit, a half word unit, a word unit and a double word unit.

### Claim 9

A processor, comprising:
circuitry to generate a compressed trace stream with a dynamic unit width indicator and a value block; and
a port to route the compressed trace stream.

### Claim 10 (depends on 9)

The processor of claim 9 wherein the dynamic unit width indicator includes an address/data width indicator qualified by a fixed unit indicator.

### Claim 11 (depends on 10)

The method of claim 10 wherein the value block has a width that is a function of the address/data width indicator and the unit indicator.

### Claim 12 (depends on 10)

The method of claim 10 wherein the unit indicator is selected from a byte unit, a half word unit, a word unit and a double word unit.

### Claim 13 (depends on 9)

The processor of claim 9 wherein the processor is embodied in hardware description language software.

### Claim 14 (depends on 13)

The processor of claim 13 wherein the processor is embodied in one of Verilog hardware description language software and VHDL hardware description language software.

### Claim 15

A system, comprising:
a processor to form a compressed trace stream with a dynamic unit width indicator and a value block; and
a probe to receive the compressed trace stream.

### Claim 16 (depends on 15)

The system of claim 15 wherein the probe routes a trace on signal to the processor.

### Claim 17 (depends on 15)

The system of claim 15 wherein the probe generates a stall signal for application to the processor.

### Claim 18 (depends on 15)

The system of claim 15 further comprising a memory and memory control circuitry within the probe.

### Claim 19 (depends on 18)

The system of claim 18 further comprising a probe interface block connected to the memory and memory control circuitry.

### Claim 20

A probe, comprising:
a memory; and
an instruction trace control block to transform a fixed unit width trace stream to a compressed trace stream with a dynamic unit width indicator and value block.

### Claim 21 (depends on 20)

The probe of claim 20 wherein the instruction trace control block processes a trace on signal.

### Claim 22 (depends on 20)

The probe of claim 20 wherein the instruction trace control block generates a stall signal.

### Claim 23 (depends on 20)

The probe of claim 20 further comprising a memory and memory control circuit connected to the instruction trace control block.