# US 2013/0159771 A1 · Accelerated Processing Unit Debugging Using a Graphics Processing Unit Centric Debug Core

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- Number: US 2013/0159771 A1
- Document ID: US20130159771A1
- Status: Published application
- Kind: A1
- Application number: 13/325,607
- Filed: 2011-12-14
- Published: 2013-06-20
- Earliest claimed: 2011-12-14
- Assignees: ATI Technologies ULC
- Inventors: Navin Patel
- Web page: https://patentgrep.com/patent/US20130159771A1

## CPC

- G06F 11/3648: {using additional hardware}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An Accelerated Processing Unit (APU) comprising a central processing unit (CPU) core portion and a graphics processing unit (GPU) core portion coupled to the CPU core portion. The GPU core portion includes a GPU core and a dedicated GPU debugging core, the dedicated GPU debugging core enabling performance of GPU centric debug functions.

## Claims

### Claim 1

A method for providing enhanced debugging capabilities comprising:
providing a graphics processing unit (GPU) core with a dedicated GPU debugging core; and,
using the dedicated GPU debugging core to perform GPU centric debug functions.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
displaying output from the GPU centric debug core on a display.

### Claim 3 (depends on 1)

The method of claim 1 wherein:
the GPU centric debug functions arbitrate states of each accompanying CPU core.

### Claim 4 (depends on 1)

The method of claim 1 wherein:
the GPU centric debug functions directly host and debug keyboard and mouse activity.

### Claim 5 (depends on 1)

The method of claim 1 wherein:
the GPU centric debug core interacts within the GPU core and connects directly to a secure processing unit (SPU) core component firmware for instructions.

### Claim 6 (depends on 5)

The method of claim 5 wherein:
the SPU core maintains operation when the APU processor is powered down; and,
the SPU core handles access restrictions for protected memory and handle GPU based resister debugging.

### Claim 7

An apparatus for providing enhanced debugging capabilities comprising:
a graphics processing unit (GPU) core portion, the GPU core portion comprising a GPU core and a dedicated GPU debugging core, the dedicated GPU debugging core enabling performance of GPU centric debug functions.

### Claim 8 (depends on 7)

The apparatus of claim 7 further comprising:
displaying output from the GPU centric debug core on a display via the GPU core portion.

### Claim 9 (depends on 7)

The apparatus of claim 7 wherein:
the GPU centric debug functions arbitrate states of each accompanying CPU core.

### Claim 10 (depends on 7)

The apparatus of claim 7 wherein:
the GPU centric debug functions directly host and debug keyboard and mouse activity.

### Claim 11 (depends on 7)

The apparatus of claim 7 wherein:
the GPU centric debug core interacts within the GPU core and connects directly to a secure processing unit (SPU) core component firmware for instructions.

### Claim 12 (depends on 11)

The apparatus of claim 11 wherein:
the SPU core is not powered down when the APU processor is powered down; and,
the SPU core handles access restrictions for protected memory and handle GPU based resister debugging.

### Claim 13

An Accelerated Processing Unit (APU) comprising:
a central processing unit (CPU) core portion;
a graphics processing unit (GPU) core portion coupled to the CPU core portion, the GPU core portion comprising a GPU core and a dedicated GPU debugging core, the dedicated GPU debugging core enabling performance of GPU centric debug functions.

### Claim 14 (depends on 13)

The APU of claim 13 wherein:
output from the GPU centric debug core is presented on a display via the GPU core portion.

### Claim 15 (depends on 13)

The APU of claim 13 wherein:
the GPU centric debug functions arbitrate states of each accompanying CPU core.

### Claim 16 (depends on 13)

The APU of claim 13 wherein:
the GPU centric debug functions directly host and debug keyboard and mouse activity.

### Claim 17 (depends on 13)

The APU of claim 13 wherein:
the GPU centric debug core interacts within the GPU core and connects directly to a secure processing unit (SPU) core component firmware for instructions.

### Claim 18 (depends on 17)

The APU of claim 17 wherein:
the SPU core is not powered down when the APU processor is powered down and
the SPU core handles access restrictions for protected memory and handle GPU based resister debugging.

### Claim 19

A computer readable media, the computer readable media comprising instructions for:
providing a graphics processing unit (GPU) core with a dedicated GPU debugging core; and,
using the dedicated GPU debugging core to perform GPU centric debug functions.

### Claim 20 (depends on 19)

The computer readable media of claim 19 further comprising instructions for:
displaying output from the GPU centric debug core on a display.

### Claim 21 (depends on 19)

The computer readable media of claim 19 wherein:
the GPU centric debug functions arbitrate states of each accompanying CPU core.

### Claim 22 (depends on 19)

The computer readable media of claim 19 wherein:
the GPU centric debug functions directly host and debug keyboard and mouse activity.

### Claim 23 (depends on 19)

The computer readable media of claim 19 wherein:
the GPU centric debug core interacts within the GPU core and connects directly to a secure processing unit (SPU) core component firmware for instructions.

### Claim 24 (depends on 23)

The computer readable media of claim 23 wherein:
the SPU core maintains operation when the APU processor is powered down; and,
the SPU core handles access restrictions for protected memory and handle GPU based resister debugging.