# US 2013/0159757 A1 · Memory array clock gating scheme

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- Number: US 2013/0159757 A1
- Document ID: US20130159757A1
- Status: Published application
- Kind: A1
- Application number: 13/331,679
- Filed: 2011-12-20
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: Oracle International Corporation
- Inventors: HEECHOUL PARK; SONG KIM; JUNGYONG LEE
- Web page: https://patentgrep.com/patent/US20130159757A1

## CPC

- G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G11C 7/106: {Data output latches}
- G11C 7/1087: {Data input latches}
- G11C 7/1093: {Input synchronization}
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 15/00: Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Dynamic power consumption is reduced by clock gating registers that synchronize memory input signals in an embedded memory array. Where a memory enable signal associated with a memory interface input signal does not meet setup timing for clock gating input registers of the memory interface signal, a clock gate enable signal may be generated prior to evaluation of the memory enable signal. The clock gate enable signal includes all functions of the memory enable signal and additional conditions because it is generated prior to evaluation of conditions on which the memory enable signal may depend. Pre-evaluated clock gate enable signals may be generated within a processor core and used to clock gate read address registers, write address registers, data input registers, and/or CAM reference address registers of an embedded memory array.

## Claims

### Claim 1

A processing device, comprising:
a processing component that receives a system clock signal and is operable to process instructions synchronously with the system clock signal;
a memory component coupled to the processing component through a memory control interface, the memory component receiving the system clock signal and including a sequential element that registers a memory control signal of the memory control interface based on a gated system clock signal; and
a clock gating element that receives the system clock signal and a clock gate enable signal, the clock gating element controlled by the clock gate enable signal to generate the gated system clock signal, the clock gate enable signal coupled to the processing component,
wherein the processing component processes an instruction associated with a predetermined memory operation, the processing component generating a clock enable value for the clock gate enable signal associated with the instruction prior to an execution stage of an instruction processing sequence.

### Claim 2 (depends on 1)

The processing device of claim 1, wherein the memory component performs a predetermined memory operation based on a memory enable signal input of the memory component, and wherein the processing component generates a memory operation value for the memory enable signal at the execution stage of the instruction processing sequence.

### Claim 3 (depends on 2)

The processing device of claim 2, wherein the processing component generates an asserted clock enable value for the clock gate enable signal associated with the instruction at a pre-execution stage of the instruction processing sequence based on a determination that the instruction is associated with the predetermined memory operation.

### Claim 4 (depends on 3)

The processing device of claim 3, wherein processing of the instruction is terminated prior to the execution stage of the instruction processing sequence based on evaluation of a specified condition.

### Claim 5 (depends on 1)

The processing device of claim 1, wherein the memory control signal comprises a read address bus and the clock gate enable signal is generated based on a determination that the instruction is associated with a memory read operation.

### Claim 6 (depends on 5)

The processing device of claim 5, wherein the memory component performs the memory read operation based on a read enable signal, the read enable signal being asserted by the processing component at the execution stage.

### Claim 7 (depends on 1)

The processing device of claim 1, wherein the memory control signal comprises a write address bus and the clock gate enable signal is generated based on a determination that the processing instruction is associated with a memory write operation.

### Claim 8 (depends on 7)

The processing device of claim 7, wherein the memory component performs the memory write operation based on a write enable signal, the write enable signal being asserted by the processing component at the execution stage.

### Claim 9 (depends on 1)

The processing device of claim 1, wherein the memory component comprises a content addressable memory and the memory control signal comprises a memory reference address bus, and wherein the clock gate enable signal is generated based on a determination that the processing instruction is associated with a content match operation.

### Claim 10 (depends on 9)

The processing device of claim 9, wherein the memory component performs the content match operation based on a content addressable memory enable signal, the content addressable memory enable signal being asserted by the processing component at the execution stage.

### Claim 11

A method for reducing power consumption in a processing device including a processor component and a memory component, the processing component and the memory component synchronized with a system clock, the method comprising:
processing an instruction within the processor component, the instruction associated with a predetermined memory operation;
generating a clock enable value associated with one or more memory interface signals for the instruction, the clock gate enable value generated for the instruction prior to an execution stage of an instruction processing sequence;
driving the clock enable value to a clock gate enable signal associated with the one or more memory interface signals; and
receiving the clock gate enable signal at a clock gate element and generating a gated system clock based on the clock gate enable signal and the system clock, the one or more memory interface signals synchronized by the gated system clock.

### Claim 12 (depends on 11)

The method of claim 11, further including generating a memory operation enable value for a memory operation enable signal associated with the predetermined memory operation at the execution stage of the instruction processing sequence.

### Claim 13 (depends on 12)

The method of claim 12, wherein the predetermined memory operation comprises a memory read operation and the one or more memory interface signals comprise a read address bus.

### Claim 14 (depends on 12)

The method of claim 12, wherein the predetermined memory operation comprises a memory write operation and the one or more memory interface signals comprise a write address bus.

### Claim 15 (depends on 12)

The method of claim 12, wherein the predetermined memory operation comprises a memory write operation and the one or more memory interface signals comprise a data input bus.

### Claim 16 (depends on 12)

The method of claim 12, wherein the predetermined memory operation comprises a content addressable memory operation and the one or more memory interface signals comprise a reference address bus.

### Claim 17 (depends on 12)

The method of claim 12, wherein the memory operation enable value comprises a non-asserted signal value based on a determination that processing of the instruction is to be terminated prior to the execution stage of the instruction processing sequence.

### Claim 18

A computer system, comprising:
a processor for synchronously processing instructions according to an instruction processing sequence, wherein processing an instruction includes determining a memory access operation associated with the instruction, the processing further including computing a memory operation enable signal based at an execution stage of the instruction processing sequence;
a memory component coupled to the processor through a memory control interface; and
a clock gating signal associated with one or more memory interface signals of the memory control interface, the one or more memory interface signals associated with the memory access operation, wherein a clock gate enable value for the clock gating signal is computed prior to the execution stage of the instruction processing sequence.

### Claim 19 (depends on 18)

The method of claim 18, wherein the computing of the clock gate enable value is based on the determining of the memory access operation associated with the instruction, and wherein the determining of the memory access operation is based on determining that the instruction is included in a predetermined set of instructions associated with the memory access operation.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
receiving the clock gating signal at the memory component; and
generating a gated clock signal that synchronizes input registers for the one or more memory interface signals based on the clock gating signal and a system clock.