# US 2013/0159692 A1 · Electronic apparatus and bios updating apparatus thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159692 A1 - Document ID: US20130159692A1 - Status: Published application - Kind: A1 - Application number: 13/671,569 - Filed: 2012-11-08 - Published: 2013-06-20 - Earliest claimed: 2011-12-16 - Assignees: ASMedia Technology Inc. - Inventors: Chih-Wei Hu; Lin-Hung Chen - Web page: https://patentgrep.com/patent/US20130159692A1 ## CPC - G06F 8/656: while running - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An electronic apparatus including a central processing unit (CPU), a chipset, a first interface circuit, a temporary memory, a BIOS (basic input/output system) memory, a second interface circuit and a first switcher is provided. The chipset is coupled to the CPU and the first switcher. The temporary memory is coupled to the first switcher and the first interface circuit. The first interface circuit is coupled to the electronic apparatus and an extended storage including a first BIOS. The second interface circuit is coupled to the first switcher and the BIOS memory. If the first BIOS is stored in the temporary memory, the temporary memory is coupled to the chipset by the first switcher; if the first BIOS is not stored in the temporary memory, the second interface circuit is coupled to the chipset by the first switcher. The electronic device can safely updates the BIOS. ## Claims ### Claim 1 A basic input/output system (BIOS) updating apparatus suitable for an electronic apparatus which has a BIOS memory and a chipset, comprising: a first interface circuit; a temporary memory coupled to the first interface circuit, when an extended storage is connected to the first interface circuit, a first BIOS in the extended storage is stored in the temporary memory by the first interface circuit; a second interface circuit connected to the BIOS memory, wherein the BIOS memory has a second BIOS; and a first switcher, a first selection terminal coupled to the temporary memory, a second selection terminal coupled to the second interface circuit, a common terminal coupled to the chipset; if the first BIOS is stored in the temporary memory, then the temporary memory is coupled to the chipset by the first switcher; if the first BIOS is not stored in the temporary memory, then the second interface circuit is coupled to the chipset by the first switcher. ### Claim 2 (depends on 1) The BIOS updating apparatus according to claim 1, further comprising a button, when the button is pressed, a first BIOS in the extended storage is transmit to the temporary memory by the first interface circuit. ### Claim 3 (depends on 1) The BIOS updating apparatus according to claim 1, when the extended storage is connected to the first interface circuit, the BIOS updating apparatus further comprising a microcontroller confirming if the first BIOS is valid for the first BIOS to be stored in the temporary memory. ### Claim 4 (depends on 3) The BIOS updating apparatus according to claim 3, further comprising a second button, when the second button is pressed, the second BIOS in the BIOS memory is updated with the first BIOS. ### Claim 5 (depends on 1) The BIOS updating apparatus according to claim 1, wherein the first interface circuit includes a universal serial bus (USB) host controller, and the extended storage is a USB storage. ### Claim 6 (depends on 1) The BIOS updating apparatus according to claim 1, wherein the temporary memory is a volatile memory. ### Claim 7 (depends on 1) The BIOS updating apparatus according to claim 1, when the extended storage is connected to the first interface circuit, the chipset is in an disable mode. ### Claim 8 An electronic apparatus, comprising: a central processing unit (CPU); a chipset coupled to the CPU; a first interface circuit; a temporary memory coupled to the first interface circuit, when an extended storage is connected to the first interface circuit, then a first BIOS in the extended storage is stored in the temporary memory by the first interface circuit; a BIOS memory having a second BIOS; a second interface circuit coupled to the BIOS memory; and a first switcher, a first selection terminal coupled to the temporary memory, a second selection terminal coupled to the second interface circuit, a common terminal coupled to the chipset; if the first BIOS is stored in the temporary memory, then the temporary memory is coupled to the chipset by the first switcher; if the first BIOS is not stored in the temporary memory, then the second interface circuit is coupled to the chipset by the first switcher. ### Claim 9 (depends on 8) The electronic apparatus according to claim 8, further comprising a button, when the button is pressed, a first BIOS in the extended storage is transmit to the temporary memory by the first interface circuit. ### Claim 10 (depends on 8) The electronic apparatus according to claim 8, when the extended storage is connected to the first interface circuit, the BIOS updating apparatus further comprising a microcontroller confirming if the first BIOS is valid, then the first BIOS is stored in the temporary memory. ### Claim 11 (depends on 10) The electronic apparatus according to claim 10, further comprising a second button, when the second button is pressed, the second BIOS in the BIOS memory is updated with the first BIOS. ### Claim 12 (depends on 8) The electronic apparatus according to claim 8, wherein the first interface circuit comprises a USB host controller, and the extended storage is a USB storage. ### Claim 13 (depends on 8) The electronic apparatus according to claim 8, wherein the temporary memory is a volatile memory. ### Claim 14 (depends on 8) The electronic apparatus according to claim 8, further comprising: a second switcher, a first selection terminal coupled to the first interface circuit, a second selection terminal coupled to the chipset, a common terminal couples to the extended storage; if the chipset is in a normal mode, then the extended storage is coupled to the chipset by the second switcher; if the chipset is in an disable mode, then the extended storage is coupled to the first interface circuit by the second switcher.