# US 2013/0159683 A1 · Instruction predication using instruction address pattern matching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159683 A1 - Document ID: US20130159683A1 - Status: Published application - Kind: A1 - Application number: 13/328,185 - Filed: 2011-12-16 - Published: 2013-06-20 - Earliest claimed: 2011-12-16 - Assignees: International Business Machines Corporation - Inventors: Mark J. Hickey; Adam J. Muff; Matthew R. Tubbs; Charles D. Wait - Web page: https://patentgrep.com/patent/US20130159683A1 ## CPC - G06F 9/30072: {to perform conditional operations, e.g. using predicates or guards} - G06F 9/30018: {Bit or string instructions} - G06F 9/30038: {using a mask} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A particular method includes receiving, at a processor, an instruction and an address of the instruction. The method also includes preventing execution of the instruction based at least in part on determining that the address is within a range of addresses. ## Claims ### Claim 1 A method, comprising: receiving, at a processor, an instruction and an address of the instruction; and preventing execution of the instruction based at least in part on determining that the address is within a range of addresses. ### Claim 2 (depends on 1) The method of claim 1, wherein the processor comprises: a match register that stores an address pattern corresponding to the range of addresses; and a mask register that identifies one or more bits of the address to be compared to the address pattern, wherein determining that the address is within the range of addresses comprises determining that the one or more bits of the address match the address pattern. ### Claim 3 (depends on 1) The method of claim 1, wherein the processor comprises a plurality of match registers storing a plurality of address patterns and wherein determining that the address is within the range of addresses comprises determining that one or more bits of the address match at least one of the plurality of address patterns. ### Claim 4 (depends on 1) The method of claim 1, further comprising executing the instruction when the address is outside the range of addresses. ### Claim 5 (depends on 1) The method of claim 1, further comprising preventing execution of the instruction based at least in part on determining that a first value stored in a count register of the processor is greater than zero. ### Claim 6 (depends on 5) The method of claim 5, further comprising: decrementing the first value in the count register to produce a second value in the count register; receiving a second instruction; and executing the second instruction independent of the range of addresses in response to determining that the second value is less than or equal to zero. ### Claim 7 (depends on 1) The method of claim 1, wherein preventing execution of the instruction comprises de-asserting a predicated instruction valid signal that is input to an execution unit of the processor. ### Claim 8 An apparatus, comprising: a processor including predication logic configured to: receive an address of an instruction; and prevent execution of the instruction based at least in part on determining that the address is within a range of addresses. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the predication logic comprises: a match register that stores an address pattern corresponding to the range of addresses; and a mask register that identifies one or more bits of the address to be compared to the address pattern. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein determining that the address is within the range of addresses comprises determining that the one or more bits of the address identified by the mask register match the address pattern stored in the match register. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein determining that the one or more bits of the address identified by the mask register match the address pattern stored in the match register comprises, for each bit in the address: performing a NAND operation on the bit in the address and the corresponding bit in the mask register; performing an AND operation on the corresponding bit in the mask register and the corresponding bit in the match register; and performing an XNOR operation on an output of the NAND operation and on an output of the AND operation. ### Claim 12 (depends on 8) The apparatus of claim 8, wherein the predication logic comprises a plurality of match registers storing a plurality of address patterns and wherein determining that the address is within the range of addresses comprises determining that one or more bits of the address match at least one of the plurality of address patterns. ### Claim 13 (depends on 8) The apparatus of claim 8, wherein the predication logic is further configured to: prevent execution of the instruction when the address is within the range of addresses and when a value stored in a count register is greater than zero; execute the instruction independent of the range of addresses when the value stored in the count register is less than or equal to zero; and decrement the value stored in the count register in response to determining whether to execute the instruction. ### Claim 14 (depends on 8) The apparatus of claim 8, further comprising an execution unit configured to execute instructions, wherein the predication logic is configured to output a predicated instruction valid signal to the execution unit, the predicated instruction valid signal indicating whether the instruction is to be executed by the execution unit. ### Claim 15 (depends on 8) The apparatus of claim 8, wherein the processor further comprises instruction decode logic configured to receive and decode the instruction. ### Claim 16 (depends on 8) The apparatus of claim 8, wherein the predication logic is integrated into an auxiliary execution unit and wherein the predication logic is coupled to one or more execution blocks. ### Claim 17 A computer program product comprising a computer readable storage medium having computer readable program code embodied therein, the computer readable program code configured to: receive an instruction and an address of the instruction; and prevent execution of the instruction based at least in part on determining that the address is within a range of addresses based on whether one or more bits of the address match at least one pattern corresponding to the range of addresses. ### Claim 18 (depends on 16) The computer program product of claim 16, wherein the computer readable program code is further configured to execute the instruction when the address is outside the range of addresses. ### Claim 19 (depends on 16) The computer program product of claim 16, wherein the computer readable program code is further configured to: prevent execution of the instruction when the address is within the range of addresses and when a count variable is greater than zero; and execute the instruction independent of the range of addresses when the count variable is less than or equal to zero. ### Claim 20 (depends on 19) The computer program product of claim 19, wherein the computer readable program code is further configured to decrement the value of the count variable in response to determining whether to execute the instruction.