# US 2013/0159674 A1 · Instruction predication using instruction filtering > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159674 A1 - Document ID: US20130159674A1 - Status: Published application - Kind: A1 - Application number: 13/329,575 - Filed: 2011-12-19 - Published: 2013-06-20 - Earliest claimed: 2011-12-19 - Assignees: International Business Machines Corporation - Inventors: Adam J. Muff; Paul E. Schardt; Robert A. Shearer; Matthew R. Tubbs - Web page: https://patentgrep.com/patent/US20130159674A1 ## CPC - G06F 9/30072: {to perform conditional operations, e.g. using predicates or guards} - G06F 9/30101: {Special purpose registers} - G06F 9/30185: {according to one or more bits in the instruction, e.g. prefix, sub-opcode} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method and circuit arrangement for selectively predicating instructions in an instruction stream based upon a predication filter criteria defined by a predication filter, which describes types or patterns of instructions that should be predicated. Predication logic compares a respective instruction of an instruction stream to predication filter criteria to determine whether the respective instruction matches the predication filter criteria, and the respective instruction is selectively predicated based on whether the respective instruction matches the predication filter criteria. ## Claims ### Claim 1 A method of executing an instruction in a processor including predication logic coupled to instruction decode logic, wherein the predication logic includes a mask register, a match register and a counter register, the method comprising: executing a least one instruction to store mask data in the mask register, match data in the match register, and a count value in the counter register; in parallel with decoding a respective instruction for execution, masking the respective instruction using the mask data to generate a masked portion of the respective instruction, comparing the masked portion of the respective instruction to the match data to determine whether the masked portion of the instruction matches the match data, and determining whether the counter register is greater than zero; in response to determining that the counter register is greater than zero and determining that the masked portion of the instruction matches the match data, communicating a first predication signal indicating that that the instruction should be predicated to an execution unit of the processor and decrementing the counter register; and in response to the execution unit receiving the first predication signal, predicating the instruction. ### Claim 2 A method of executing an instruction in a processor, the method comprising: in parallel with decoding an instruction for execution, comparing the instruction with a predication filter to determine whether the instruction matches a predication filter criteria defined by the predication filter; and selectively predicating the instruction in response to determining that the instruction matches the predication filter criteria. ### Claim 3 (depends on 2) The method of claim 2, wherein selectively predicating the instruction includes transmitting a predication signal to an issue logic of the processor, the predication signal indicating whether to predicate the instruction. ### Claim 4 (depends on 2) The method of claim 2, wherein the predication filter includes a match register storing match data, wherein comparing the instruction with a predication filter includes comparing the instruction with the match data, and wherein determining whether the instruction matches the predication filter criteria is based at least in part on whether at least a portion of the instruction matches the match data. ### Claim 5 (depends on 4) The method of claim 4, further comprising: prior to comparing the instruction with the predication filter to determine whether the instruction matches the predication filter criteria, storing match data in the match register. ### Claim 6 (depends on 4) The method of claim 4, wherein the match data corresponds to at least a portion of a primary opcode. ### Claim 7 (depends on 4) The method of claim 4, wherein the match data corresponds to at least a portion of a secondary opcode. ### Claim 8 (depends on 4) The method of claim 4, wherein the match data corresponds to at least a portion of a register address. ### Claim 9 (depends on 4) The method of claim 4, further comprising: in response to at least a portion of the instruction matching the match data, determining whether a counter value stored in a counter register associated with the predication filter is greater than zero, and wherein selectively predicating the instruction is based at least in part on determining that the counter value is greater than zero. ### Claim 10 (depends on 4) The method of claim 4, wherein the predication filter includes a mask register storing mask data, wherein comparing the instruction with a predication filter includes masking the instruction with the mask data to generate a masked portion of the instruction, and wherein the at least a portion of the instruction corresponds to the masked portion. ### Claim 11 (depends on 10) The method of claim 10, further comprising: prior to comparing the instruction with the predication filter to determine whether to predicate the instruction matches the predication filter criteria, storing mask data in the mask register. ### Claim 12 (depends on 10) The method of claim 10, wherein the instruction includes a primary opcode portion, and wherein the mask data is configured to mask the instruction such that the masked portion of the instruction includes at least a portion of the primary opcode portion of the instruction. ### Claim 13 (depends on 10) The method of claim 10, wherein the instruction includes a secondary opcode portion, and wherein the mask data is configured to mask the instruction such that the masked portion of the instruction includes at least a portion of the secondary opcode portion of the instruction. ### Claim 14 (depends on 10) The method of claim 10, wherein the instruction includes a register address portion, and wherein the mask data is configured to mask the instruction such that the masked portion of the instruction includes at least a portion of the register address portion of the instruction. ### Claim 15 (depends on 2) The method of claim 2, wherein comparing the instruction with the predication filter includes determining a counter value stored in a counter register associated with the predication filter, and wherein selectively predicating the instruction is based at least in part on the counter value. ### Claim 16 (depends on 15) The method of claim 15, further comprising decrementing the counter value in response to predicating the instruction. ### Claim 17 (depends on 15) The method of claim 15, further comprising decrementing the counter value in response to decoding the instruction. ### Claim 18 A circuit arrangement, comprising: a processing unit; decode logic disposed in the processing unit and configured to decode an instruction; and predication logic disposed in the processing unit and configured to compare the instruction with a predication filter in parallel with decoding the instruction to determine whether the instruction matches a predication filter criteria defined by the predication filter, and to selectively predicate the instruction in response to the determination. ### Claim 19 (depends on 18) The circuit arrangement of claim 18, wherein the predication logic includes a match register storing match data, wherein the predication logic is configured to compare the instruction with the predication filter by comparing the instruction with the match data, and wherein the predication logic determines whether the instruction matches the predication filter criteria based at least in part on whether at least a portion of the instruction matches the match data. ### Claim 20 (depends on 19) The circuit arrangement of claim 19, wherein the predication logic is includes a counter register configured to store a count value, wherein the predication logic is configured to determine whether the counter register is greater than zero in response to determining that at least a portion of the instruction matches the match data, and wherein the predication logic selectively predicates the instruction based at least in part on whether the counter register is greater than zero. ### Claim 21 (depends on 19) The circuit arrangement of claim 19, wherein the predication logic includes a mask register storing mask data, wherein the predication logic is configured to compare the instruction with the predication filter by masking the instruction with the mask data to generate a masked portion of the instruction, and wherein the at least a portion of the instruction corresponds to the masked portion. ### Claim 22 (depends on 18) An integrated circuit device comprising the circuit arrangement of claim 18. ### Claim 23 (depends on 18) A program product comprising a computer readable medium and logic definition program code resident on the computer readable medium and defining the circuit arrangement of claim 18.