# US 2013/0159673 A1 · Providing capacity guarantees for hardware transactional memory systems using fences > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159673 A1 - Document ID: US20130159673A1 - Status: Published application - Kind: A1 - Application number: 13/327,657 - Filed: 2011-12-15 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: Advanced Micro Devices, Inc. - Inventors: Martin T. Pohlack; Michael Hohmuth; Stephan Diestelhorst; David Christie; Luke Yen - Web page: https://patentgrep.com/patent/US20130159673A1 ## CPC - G06F 9/30087: {Synchronisation or serialisation instructions} - G06F 9/3842: {Speculative instruction execution} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method is provided that includes determining a number of outstanding out-of-order instructions in an instruction stream. The method includes determining a number of available hardware resources for executing out-of-order instructions and inserting fencing instructions into the instruction stream if the number of outstanding out-of-order instructions exceeds the determined number of available hardware resources. A second method is provided for compiling source code that includes determining a speculative region. The second method includes generating machine-level instructions and inserting fencing instructions into the machine-level instructions in response to determining the speculative region. A processing device is provided that includes cache memory and a processing unit to execute processing device instructions in an instruction stream. The processing device includes an out-of-order speculation supervisor unit to determine hardware resource availability and generate an indication to insert fencing instructions in response to the availability. Computer readable storage media are also provided. ## Claims ### Claim 1 A method, comprising: determining a number of outstanding out-of-order instructions in an instruction stream to be executed by a processing device; determining a number of hardware resources available for executing out-of-order instructions; and inserting at least one fencing instruction into the instruction stream in response to determining the number of outstanding out-of-order instructions exceeds the determined number of available hardware resources. ### Claim 2 (depends on 1) The method of claim 1, wherein the at least one fencing instruction is at least one of a dedicated fencing micro-instruction or a non-fencing micro-instruction modified to comprise a fencing indication. ### Claim 3 (depends on 1) The method of claim 1, wherein inserting at least one fencing instruction comprises inserting a plurality of fencing instructions into the instruction stream at a determined interval. ### Claim 4 (depends on 1) The method of claim 1, further comprising: determining a decrease in the number of available hardware resources; and increasing a number of fencing instructions inserted per number of instructions in the instruction stream in response to the determined decrease of in the number of available hardware resources. ### Claim 5 (depends on 1) The method of claim 1, further comprising: determining an increase in the number of available hardware resources; and decreasing a number of fencing instructions inserted per number of instructions in the instruction stream in response to the determined increase in the number of available of hardware resources. ### Claim 6 (depends on 1) The method of claim 1, further comprising at least one of: wherein the at least one fencing instruction is inserted into the instruction stream at a decoding stage; and wherein the at least one fencing instruction is inserted into the instruction stream at a pipelining stage. ### Claim 7 (depends on 1) The method of claim 1, wherein inserting the fencing instruction into the instruction stream comprises: receiving an indication to include fencing instructions in the instruction stream; and inserting the at least one fencing instruction in response to the received indication. ### Claim 8 (depends on 1) The method of claim 1, further comprising: compiling a portion of source code; generating a plurality of machine-level instructions based at least on the portion of source code; and inserting at least one fencing instruction into the plurality of machine-level instructions in response to determining a speculative region in the portion of source code. ### Claim 9 A method, comprising: compiling a portion of source code, comprising: determining a speculative region associated with the portion of source code; generating a plurality of machine-level instructions based at least on the portion of source code; and inserting at least one fencing instruction into the plurality of machine-level instructions in response to determining the speculative region. ### Claim 10 (depends on 9) The method of claim 9, wherein the fencing instruction is at least one of a dedicated fencing machine-level instruction or a non-fencing machine-level instruction modified to comprise a fencing indication. ### Claim 11 (depends on 9) The method of claim 9, wherein inserting the at least one fencing instruction comprises inserting a plurality of fencing instructions into the plurality of machine-level instructions at a determined interval. ### Claim 12 (depends on 9) The method of claim 9, further comprising: determining a runtime model of the plurality of machine-level instructions; and wherein inserting the at least one fencing instruction into the plurality of machine-level instructions is based at least upon the determined runtime model. ### Claim 13 (depends on 12) The method of claim 12, further comprising at least one of: decreasing the number of fencing instructions inserted in response to a model-based indication of available hardware capacity; and increasing the number of fencing instructions inserted in response to the model-based indication of available hardware capacity. ### Claim 14 (depends on 12) The method of claim 12, wherein the runtime model comprises at least one of: determining a memory access address offset of at least one variable in the portion of source code; determining a memory access address of at least one object or data structure; and determining at least one memory access address of one or more indices in an array of variables. ### Claim 15 (depends on 9) The method of claim 9, further comprising: defining a hardware capacity model associated with a micro-processor architecture based at least upon a performance characteristic; inserting the at least one fencing instruction based upon the hardware capacity model; and increasing the number of fencing instructions inserted in response to a runtime determination of a decrease in available hardware capacity. ### Claim 16 (depends on 9) The method of claim 9, further comprising: determining a number of available hardware resources associated with a processing device; and inserting at least one fencing instruction into an instruction stream associated with the processing device in response to determining the number available hardware resources. ### Claim 17 A processing device that comprises: at least one cache memory; at least one processing unit, communicatively coupled to the at least one cache memory, being adapted to execute one or more processing device instructions in an instruction stream; and an out-of-order speculation supervisor unit adapted to determine an availability of at least one hardware resource associated with the processing device, and adapted to generate an indication to insert a fencing instruction in response to the determined availability. ### Claim 18 (depends on 17) The processing device of claim 17, further comprising: a decode unit communicatively coupled to the at least one processing unit and to the out-of-order speculation supervisor unit; and wherein the decode unit is adapted to receive the fencing indication from the out-of-order speculation supervisor unit and adapted to insert a fencing instruction into the instruction stream. ### Claim 19 (depends on 17) The processing device of claim 17, further comprising: an instruction pipeline unit communicatively coupled to the at least one processing unit and to the out-of-order speculation supervisor unit; and wherein the instruction pipeline unit includes an issue stage adapted to receive an inserted fencing instruction based at least upon the fencing indication. ### Claim 20 A non-transitory, computer-readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create an apparatus, wherein the apparatus comprises: at least one cache memory; at least one processing unit, communicatively coupled to the at least one cache memory, being adapted to execute one or more processing device instructions in an instruction stream; and an out-of-order speculation supervisor unit adapted to determine an availability of at least one hardware resource associated with the processing device, and adapted to generate an indication to insert a fencing instruction in response to the determined availability. ### Claim 21 (depends on 20) The non-transitory, computer-readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create an apparatus as in claim 20, wherein the apparatus further comprises: a decode unit communicatively coupled to the at least one processing unit and to the out-of-order speculation supervisor unit; and wherein the decode unit is adapted to receive the fencing indication from the out-of-order speculation supervisor unit and adapted to insert a fencing instruction into the instruction stream. ### Claim 22 (depends on 20) The non-transitory, computer-readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create an apparatus as in claim 20, wherein the apparatus further comprises: an instruction pipeline unit communicatively coupled to the at least one processing unit and to the out-of-order speculation supervisor unit; and wherein the instruction pipeline unit includes an issue stage adapted to receive an inserted fencing instruction based at least upon the fencing indication. ### Claim 23 A non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform a method, comprising: determining a number of outstanding out-of-order instructions in an instruction stream to be executed by a processing device; determining a number of hardware resources available for executing out-of-order instructions; and inserting at least one fencing instruction into the instruction stream in response to determining the number of outstanding out-of-order instructions exceeds the determined number of available hardware resources. ### Claim 24 A non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform a method, comprising: compiling a portion of source code, comprising: determining a speculative region associated with the portion of source code; generating a plurality of machine-level instructions based at least on the portion of source code; and inserting at least one fencing instruction into the plurality of machine-level instructions in response to determining the speculative region.