# US 2013/0159672 A1 · Bitstream Buffer Manipulation With A SIMD Merge Instruction

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- Number: US 2013/0159672 A1
- Document ID: US20130159672A1
- Status: Published application
- Kind: A1
- Application number: 13/753,050
- Filed: 2013-01-29
- Published: 2013-06-20
- Earliest claimed: 2001-10-29
- Assignees: Intel Corporation
- Inventors: Yen-Kueng Chen; William W. Macy, Jr.; Matthew Holliman; Eric L. Debes; Minerva M. Yeung
- Web page: https://patentgrep.com/patent/US20130159672A1

## CPC

- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30014: {with variable precision}
- G06F 9/30018: {Bit or string instructions}
- G06F 9/30025: {Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion}
- G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30109: {having multiple operands in a single register}
- G06F 9/30112: {comprising data of variable length}
- G06F 9/3013: {according to data content, e.g. floating-point registers, address registers}
- G06F 9/3816: {Instruction alignment, e.g. cache line crossing}
- G06F 9/3885: {using a plurality of independent parallel functional units}
- G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors}
- G06F 17/147: {Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform (G06F17/145 takes precedence)}
- G06F 17/15: Correlation function computation {including computation of convolution operations (arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

## Claims

### Claim 1

A system comprising:
a processor comprising:
a plurality of registers;
an instruction decoder to decode a shift right merge instruction indicating a first 32-bit source operand and a second 32-bit source operand, the first 32-bit source operand including a first four 8-bit byte data elements, the second 32-bit source operand including a second four 8-bit byte data elements; and
an execution unit coupled with the instruction decoder and the plurality of registers, the execution unit in response to the shift right merge instruction to:
shift the second 32-bit source operand right by one byte;
merge a least significant 8-bit byte data element of the first 32-bit source operand into a most significant byte position of the shifted second 32-bit source operand to generate a result; and
store the result in a 32-bit destination indicated by the shift right merge instruction;
a Bluetooth universal asynchronous receiver/transmitter (UART) interface;
a universal serial bus (USB) interface;
a synchronous dynamic random access memory (SDRAM) control interface; and
a flash interface.

### Claim 2 (depends on 1)

The system of claim 1, wherein the execution unit, in response to the shift right merge instruction, is to shift the first 32-bit source operand left by three bytes.

### Claim 3 (depends on 1)

The system of claim 1, wherein the result includes a most significant three of the second four 8-bit byte data elements of the second 32-bit source operand in a least significant portion of the result.

### Claim 4 (depends on 1)

The system of claim 1, wherein the system comprises a handheld device.

### Claim 5 (depends on 1)

The system of claim 1, wherein the system comprises a cellular telephone.

### Claim 6 (depends on 1)

The system of claim 1, wherein the system comprises a personal digital assistant.

### Claim 7 (depends on 1)

The system of claim 1, wherein the processor comprises a SIMD coprocessor.

### Claim 8

A system comprising:
a processor comprising:
a plurality of registers, wherein the plurality of registers are to store packed data;
a cache;
an instruction fetch unit to fetch a shift right merge instruction;
an instruction decoder to decode the shift right merge instruction, the shift right merge instruction indicating a first 32-bit source operand in a register of the plurality of registers and a second 32-bit source operand in a register of the plurality of registers, the first 32-bit source operand including a first four 8-bit byte data elements, the second 32-bit source operand including a second four 8-bit byte data elements; and
an execution unit coupled with the instruction decoder and the plurality of registers, the execution unit in response to the shift right merge instruction to:
shift the second 32-bit source operand right by one byte;
merge a least significant 8-bit byte data element of the first 32-bit source operand into a most significant byte position of a result that also includes,
in a least significant portion thereof, three shifted 8-bit byte data elements of the second 32-bit source operand; and
store the result in a 32-bit destination indicated by the shift right merge instruction, wherein the destination is a register of the plurality of registers;
a Bluetooth universal asynchronous receiver/transmitter (UART) interface;
a universal serial bus (USB) interface;
a synchronous dynamic random access memory (SDRAM) control interface; and
a flash interface.

### Claim 9 (depends on 8)

The system of claim 8, wherein the execution unit, in response to the shift right merge instruction, is to shift the first 32-bit source operand left by three bytes.

### Claim 10 (depends on 8)

The system of claim 8, wherein the result includes a most significant three of the second four 8-bit byte data elements of the second 32-bit source operand in a least significant portion of the result.

### Claim 11 (depends on 8)

The system of claim 8, wherein the system comprises a handheld device.

### Claim 12 (depends on 8)

The system of claim 8, wherein the system comprises a cellular telephone.

### Claim 13 (depends on 8)

The system of claim 8, wherein the system comprises a personal digital assistant.

### Claim 14 (depends on 8)

The system of claim 8, wherein the processor comprises a SIMD coprocessor.