# US 2013/0159671 A1 · Methods and systems for detection in a state machine > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159671 A1 - Document ID: US20130159671A1 - Status: Published application - Kind: A1 - Application number: 13/327,580 - Filed: 2011-12-15 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: Micron Technology, Inc. - Inventors: David R. Brown; Harold B Noyes - Web page: https://patentgrep.com/patent/US20130159671A1 ## CPC - G06F 8/45: {Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions} - G06F 9/4498: {Finite state machines} - G06V 10/955: {using specific electronic processors} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06V: IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING ## Abstract A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D-flip flop including an output coupled to a second input of the AND gate. ## Claims ### Claim 1 A device, comprising: a state machine comprising: a plurality of blocks, each of the blocks comprising a plurality of rows, each of the rows comprising a plurality of programmable elements, each of the programmable elements comprising: a data analysis element comprising a plurality of memory cells configured to analyze at least a portion of a data stream and to output a result of the analysis; and a detection cell configured to output the result when in an active state. ### Claim 2 (depends on 1) The device of claim 1, wherein the detection cell comprises a D flip-flop coupled to an AND gate. ### Claim 3 (depends on 2) The device of claim 2, wherein the detection cell comprises a first input configured to receive the result from the data analysis element. ### Claim 4 (depends on 3) The device of claim 3, wherein the detection cell comprises a second input configured to receive an enable signal as a data input to the D flip-flop. ### Claim 5 (depends on 4) The device of claim 4, wherein the detection cell comprises a third input configured to receive a clock signal as a clock input to the D flip-flop. ### Claim 6 (depends on 5) The device of claim 5, wherein the detection cell is configured to provide an output of the D flip-flop as an input to the AND gate and provide the result from the data analysis element as a second input to the AND gate. ### Claim 7 (depends on 5) The device of claim 5, wherein the detection cell is in an active state responsive to the enable signal and the clock signal. ### Claim 8 (depends on 1) The device of claim 1, wherein the data analysis element comprises a first data analysis element, wherein the detection cell comprises a first detection cell, and wherein each of the programmable elements further comprises a second data analysis element and a second detection cell. ### Claim 9 (depends on 1) The device of claim 1, wherein each of the rows further comprises a local routing matrix coupled to the programmable elements of the respective row. ### Claim 10 (depends on 1) The device of claim 1, comprising a server, a personal computer, a work station, a router, a network switch, chip test equipment, a laptop, a cell phone, a media player, a game console, or a mainframe computer that comprises the state machine. ### Claim 11 A device, comprising: a data analysis element comprising a plurality of memory cells configured to analyze at least a portion of a data stream and to output a result of the analysis; and a detection cell comprising: an AND gate configured to receive the result as a first input; and a D-flip flop comprising an output coupled to a second input of the AND gate. ### Claim 12 (depends on 11) The device of claim 11, wherein the D flip-flop comprises a data input configured to receive an enable signal. ### Claim 13 (depends on 12) The device of claim 12, wherein the D flip-flop comprises a clock input configured to receive a clock signal. ### Claim 14 (depends on 13) The device of claim 13, wherein the D flip-flop is configured to latch the enable signal as a latched enable signal from the output of the D flip-flop in response to the clock signal. ### Claim 15 (depends on 14) The device of claim 14, wherein the AND gate is configured to output the result responsive to receiving the latched enable signal from the D flip-flop. ### Claim 16 (depends on 11) The device of claim 11, wherein the data analysis element comprises a first data analysis element, wherein the detection cell comprises a first detection cell, wherein the AND gate comprises a first AND gate, the device further comprising: a second data analysis element comprising a second plurality of memory cells configured to analyze at least a portion of a data stream and to output a result of the analysis; and a second detection cell comprising: a second AND gate configured to receive the result of an analysis performed by the second data analysis element as a first input; and a second D-flip flop comprising an output coupled to a second input of the second AND gate. ### Claim 17 (depends on 16) The device of claim 16, wherein the enable signal comprises a first enable signal and the second D flip-flop comprises a second data input configured to receive a second enable signal. ### Claim 18 (depends on 17) The device of claim 17, comprising a local routing matrix configured to selectively provide the first and the second enable signals. ### Claim 19 (depends on 16) The device of claim 16, further comprising intra-group circuitry coupled to the first and second detection cells. ### Claim 20 (depends on 19) The device of claim 19, wherein the intra-group circuitry comprises a multiplexer coupled to the outputs of the first and second AND gates. ### Claim 21 (depends on 20) The device of claim 20, wherein the intra-group circuitry further comprises an OR gate coupled to the multiplexer, wherein the OR gate is coupled to the outputs of the first and second AND gates by switching elements. ### Claim 22 A method, comprising: outputting a result of an analysis of at least a portion of a data stream from a data analysis element; receiving at an AND gate of a detection cell the result as a first input; receiving at a D flip-flop of the detection cell an enable signal and a clock signal; latching at the D flip-flop the enable signal as a latched signal in response to the clock signal; and receiving at the AND gate the latched enable signal. ### Claim 23 (depends on 22) The method of claim 22, comprising outputting from the AND gate the result in response to receiving the latched enable signal. ### Claim 24 (depends on 22) The method of claim 22, comprising receiving the enable signal from a local routing matrix coupled to the D flip-flop.