# US 2013/0159670 A1 · Counter operation in a state machine lattice

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- Number: US 2013/0159670 A1
- Document ID: US20130159670A1
- Status: Published application
- Kind: A1
- Application number: 13/327,499
- Filed: 2011-12-15
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Micron Technology, Inc.
- Inventors: Harold B Noyes; David R. Brown; Paul Glendenning
- Web page: https://patentgrep.com/patent/US20130159670A1

## CPC

- G05B 19/045: using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
- G06F 9/4498: {Finite state machines}
- G06F 15/82: data or demand driven
- G06F 21/567: {using dedicated hardware}
- G06N 5/047: Pattern matching networks; Rete networks
- H03K 19/17724: Structural details of logic blocks
- H03K 19/17748: Structural details of configuration resources
- G06F 2207/025: String search, i.e. pattern matching, e.g. find identical word or best match in a string
- G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

## Claims

### Claim 1

A device, comprising:
a finite state machine (FSM) lattice comprising:
a plurality of blocks, each of the blocks comprising a plurality of rows,
each of the rows comprising a plurality of programmable elements, wherein a particular one of the programmable elements is configured to output a signal based on a detection of a condition; and
at least one of the rows of a particular one of the blocks further comprising a counter configured to be selectively coupleable to any of the plurality of programmable elements in any of the plurality of rows of the particular one of the blocks, wherein the counter is configured to output in response to counting the condition was detected a certain number of times.

### Claim 2 (depends on 1)

The device of claim 1, wherein each of the plurality of rows of the particular one of the blocks comprises intra-row circuitry configured to selectively couple any of the plurality of programmable elements of that row with the counter.

### Claim 3 (depends on 2)

The device of claim 2, wherein each of the plurality of blocks comprises intra-block circuitry configured to selectively couple any of the plurality of rows of that block, wherein one counter in one of the plurality of rows of that block may be coupled to another counter in another one of the plurality of rows of that block.

### Claim 4 (depends on 3)

The device of claim 3, wherein the lattice comprises inter-block circuitry configured to selectively couple any of the plurality of blocks, wherein the counter in the particular one of the plurality of blocks may be selectively coupled to a programmable element in another one of the plurality of blocks via the intra-row circuitry, the intra-block circuitry, and the inter-block circuitry.

### Claim 5 (depends on 1)

The device of claim 1, wherein each counter comprises a decrementing counter.

### Claim 6 (depends on 1)

The device of claim 1, wherein the counter being configured to be selectively coupleable to any other counter in the plurality of rows comprises the counter being configured to be selectively coupleable to any other counter in the plurality of rows to form a cascaded counter.

### Claim 7 (depends on 1)

The device of claim 1, wherein each counter comprises:
a hold input configured to be asserted to hold the counter at zero responsive to the counter decrementing to zero and until the counter is reset; and
a roll input configured to be asserted to load an initial value of the counter when the hold input is not asserted.

### Claim 8 (depends on 1)

The device of claim 1, wherein each counter comprises:
an enable chain input configured to be asserted to enable the counter to be part of a cascaded counter; and
a roll input configured to be asserted to roll over an initial value of the counter responsive to the counter decrementing to zero.

### Claim 9 (depends on 8)

The device of claim 8, wherein each counter comprises a carry input configured to receive a rolled over value from a lower order counter.

### Claim 10 (depends on 9)

The device of claim 9, wherein each counter comprises a result input configured to receive an indication responsive to a higher order counter decrementing to zero.

### Claim 11 (depends on 8)

The device of claim 8, wherein the each counter comprises an enable reset input configured to be asserted by another counter to reset the counter.

### Claim 12 (depends on 11)

The device of claim 11, wherein the enable reset input comprises a plurality of enable reset inputs configured to enable the counter to be reset by any of a plurality of other counters.

### Claim 13 (depends on 1)

The device of claim 1, wherein a particular one of the plurality of rows of the particular one of the blocks not comprising a counter comprises a Boolean logic cell, wherein the Boolean logic cell is selectively coupleable to the counter via intra-row circuitry and intra-block circuitry.

### Claim 14 (depends on 1)

The device of claim 1, wherein the counter being configured to output in response to counting the condition was detected a certain number of times comprises the counter being configured to output in response to counting the condition was detected at least the certain number of times.

### Claim 15 (depends on 1)

The device of claim 1, wherein the counter being configured to output in response to counting the condition was detected a certain number of times comprises the counter being configured to output in response to counting the condition was detected exactly the certain number of times.

### Claim 16 (depends on 1)

The device of claim 1, wherein the counter being configured to output in response to counting the condition was detected a certain number of times comprises the counter being configured to output in response to counting the condition was detected within a certain range of times.

### Claim 17 (depends on 1)

The device of claim 1, wherein the counter is configured to be selectively coupleable to any other counter in the plurality of rows of the particular one of the blocks.

### Claim 18 (depends on 1)

The device of claim 1, comprising a server, a personal computer, a work station, a router, a network switch, chip test equipment, a laptop, a cell phone, a media player, a game console, or a mainframe computer that comprises the FSM lattice.

### Claim at position 19

-29. (canceled)