# US 2013/0159668 A1 · Predecode logic for autovectorizing scalar instructions in an instruction buffer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159668 A1 - Document ID: US20130159668A1 - Status: Published application - Kind: A1 - Application number: 13/330,888 - Filed: 2011-12-20 - Published: 2013-06-20 - Earliest claimed: 2011-12-20 - Assignees: International Business Machines Corporation - Inventors: Adam J. Muff; Paul E. Schardt; Robert A. Shearer; Matthew R. Tubbs - Web page: https://patentgrep.com/patent/US20130159668A1 ## CPC - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 15/8053: {Vector processors} - G06F 9/45516: {Runtime code conversion or optimisation} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A circuit arrangement, method, and program product for substituting a plurality of scalar instructions in an instruction stream with a functionally equivalent vector instruction for execution by a vector execution unit. Predecode logic is coupled to an instruction buffer which stores instructions in an instruction stream to be executed by the vector execution unit. The predecode logic analyzes the instructions passing through the instruction buffer to identify a plurality of scalar instructions that may be replaced by a vector instruction in the instruction stream. The predecode logic may generate the functionally equivalent vector instruction based on the plurality of scalar instructions, and the functionally equivalent vector instruction may be substituted into the instruction stream, such that the vector execution unit executes the vector instruction in lieu of the plurality of scalar instructions. ## Claims ### Claim 1 A method for executing scalar instructions in a processor including a vector execution unit including a plurality of processing lanes, each processing lane configured to perform an operation of a vector instruction to generate a processing lane result, and a dot product adder configured to sum the processing lane results to generate a vector instruction result, the method comprising: analyzing instructions stored in an instruction buffer associated with the processor utilizing a predecode logic coupled to the instruction buffer to identify a plurality of scalar instructions in an instruction stream for which a functionally equivalent vector instruction exists, wherein the plurality of scalar instructions includes a subset of scalar instructions generating independent results and a scalar add instruction for performing an add operation of the independent results; generating the functionally equivalent vector instruction based on the plurality of scalar instructions, wherein the vector instruction is configured to perform an operation based on each scalar instruction of the subset of scalar instructions and an add operation based on the scalar add instruction; substituting the functionally equivalent vector instruction for the plurality of scalar instructions in the instruction stream; and executing the functionally equivalent vector instruction in the vector execution unit to generate a vector instruction result by: performing each operation of the vector instruction corresponding each scalar instruction of the subset of scalar instructions with a processing lane of the vector execution unit to generate a plurality of processing lane results, and performing the add operation of the vector instruction corresponding to the scalar add instruction with the dot product adder of the vector execution unit to generate the vector instruction result. ### Claim 2 A method for executing instructions in a processor, the method comprising: analyzing instructions stored in an instruction buffer associated with the processor to identify a plurality of scalar instructions in an instruction stream for which a functionally equivalent vector instruction exists; and substituting the functionally equivalent vector instruction for the plurality of scalar instructions in the instruction stream such that the functionally equivalent vector instruction is executed by the processor in lieu of the plurality of scalar instructions. ### Claim 3 (depends on 2) The method of claim 2, wherein the plurality of scalar instructions includes a subset of instructions generating independent results and an add instruction performing an add operation of the independent results, and wherein identifying the plurality of instructions in the instruction stream is based at least in part on the add instruction performing an add operation of the independent results of the subset of instructions in the plurality of scalar instructions. ### Claim 4 (depends on 2) The method of claim 2, wherein analyzing instructions performed in the instruction buffer to identify a plurality of scalar instructions in the instruction stream is performed utilizing predecode logic coupled to the instruction buffer. ### Claim 5 (depends on 4) The method of claim 4, wherein substituting the functionally equivalent vector instruction for the plurality of scalar instructions in the instruction stream includes communicating the functionally equivalent vector instruction from the predecode logic to instruction decode logic associated with the processor in lieu of communicating the plurality of scalar instructions from the instruction buffer to the instruction decode logic. ### Claim 6 (depends on 2) The method of claim 2, further comprising: generating the functionally equivalent vector instruction utilizing predecode logic coupled to the instruction buffer based at least in part on the plurality of scalar instructions. ### Claim 7 (depends on 6) The method of claim 6, wherein the plurality of scalar instructions store at least one temporary result in a predetermining register in a register file and the functionally equivalent vector avoids storing the temporary result in the predetermined register of the register file. ### Claim 8 (depends on 7) The method of claim 7, wherein the register file comprises a predefined amount of read ports, and wherein generating the functionally equivalent vector instruction is based at least in part on the predefined amount of read ports of the register file. ### Claim 9 (depends on 6) The method of claim 6, wherein the processor includes a predefined amount of processing lanes, and wherein generating the functionally equivalent vector instruction is based at least in part on the predefined amount of processing lanes of the processor. ### Claim 10 (depends on 6) The method of claim 6, wherein each scalar instruction of the plurality of instructions includes a scalar opcode corresponding to a scalar operation to be performed by a processor in executing such instruction, and wherein generating the functionally equivalent vector instruction is based at least in part on the opcodes of each scalar instruction of the plurality of scalar instructions. ### Claim 11 (depends on 10) The method of claim 10, wherein the processor includes a plurality of processing lanes, and wherein the functionally equivalent vector instruction instructs one or more of the processing lanes to perform operations based at least in part on one or more of the scalar opcodes of the plurality of scalar instructions. ### Claim 12 A circuit arrangement, comprising: a vector execution unit configured to execute instructions, the vector instruction unit including a plurality of processing lanes, each processing lane configured to perform an operation of a vector instruction to generate a processing lane result, and a dot product adder configured to sum the processing lane results to generate a vector instruction result; an instruction buffer coupled to the vector execution unit and configured to store instructions in an instruction stream for execution by the vector execution unit; and predecode logic coupled to the instruction buffer and configured to analyze instructions stored in the instruction buffer to identify a plurality of scalar instructions in the instruction stream for which a functionally equivalent vector instruction exists, and substitute the functionally equivalent vector instruction for the plurality of scalar instructions in the instruction stream such that the functionally equivalent vector instruction is executed by the vector execution unit in lieu of the plurality of scalar instructions. ### Claim 13 (depends on 12) The circuit arrangement of claim 12, wherein the plurality of scalar instructions includes a subset of instructions generating independent results and an add instruction performing an add operation of the independent results, and wherein the predecode logic identifies the plurality of instructions in the instruction stream based at least in part on the add instruction performing an add operation of the independent results of the subset of instructions in the plurality of scalar instructions. ### Claim 14 (depends on 12) The circuit arrangement of claim 12, further comprising: decode logic coupled between the instruction buffer and the vector execution unit, the predecode logic being configured to substitute the functionally equivalent vector instruction for the plurality of scalar instructions in the instruction stream by communicating the functionally equivalent vector instruction to the decode logic. ### Claim 15 (depends on 12) The circuit arrangement of claim 12, wherein the predecode logic is further configured to generate the functionally equivalent vector instruction based at least in part on the plurality of scalar instructions. ### Claim 16 (depends on 15) The circuit arrangement of claim 15, further comprising: a register file coupled to the vector execution unit; wherein the plurality of scalar instructions includes a plurality of operand register addresses for the register file, and wherein the predecode logic is configured to generate the functionally equivalent vector instruction including the plurality of operand register addresses for the register file. ### Claim 17 (depends on 16) The circuit arrangement of claim 16, wherein the register file includes a predefined amount of read ports, and wherein the predecode logic is configured to generate the functionally equivalent vector instruction based at least in part on the predefined amount of read ports of the register file. ### Claim 18 (depends on 15) The circuit arrangement of claim 15, wherein the vector execution unit includes a predefined amount of processing lanes, and wherein the predecode logic is configured to generate the functionally equivalent vector instruction based at least in part on the predefined amount of processing lanes of the vector execution unit. ### Claim 19 (depends on 15) The circuit arrangement of claim 15, wherein each scalar instruction of the plurality of instructions includes a scalar opcode corresponding to a scalar operation to be performed by a processor in executing such instruction, and wherein the predecode logic is configured to generate the functionally equivalent instruction based at least in part on the opcode of each scalar instruction of the plurality of scalar instructions. ### Claim 20 (depends on 19) The circuit arrangement of claim 19, wherein the predecode logic is configured to generate the functionally equivalent vector instruction such that a processing lane of the vector execution unit performs an operation based at least in part on one or more of the scalar opcodes of the plurality of scalar instructions when executing the functionally equivalent vector instruction. ### Claim 21 (depends on 12) The circuit arrangement of claim 12, wherein the plurality of scalar instructions store at least one temporary result in a predetermined register in a register file and the predecode logic is configured to generate the functionally equivalent vector to avoid storing the temporary result in the predetermined register of the register file. ### Claim 22 (depends on 12) An integrated circuit device comprising the circuit arrangement of claim 12. ### Claim 23 (depends on 12) A program product comprising a computer readable medium and logic definition program code resident on the computer readable medium and defining the circuit arrangement of claim 12.