# US 2013/0159665 A1 · Specialized vector instruction and datapath for matrix multiplication

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- Number: US 2013/0159665 A1
- Document ID: US20130159665A1
- Status: Published application
- Kind: A1
- Application number: 13/327,519
- Filed: 2011-12-15
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: VeriSilicon Holdings Co., Ltd.
- Inventors: Asheesh Kashyap
- Web page: https://patentgrep.com/patent/US20130159665A1

## CPC

- G06F 15/8053: {Vector processors}
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30109: {having multiple operands in a single register}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A data processing element includes an input unit configured to provide instructions for scalar, vector and array processing, and a scalar processing unit configured to provide a scalar pipeline datapath for processing a scalar quantity. Additionally, the data processing element includes a vector processing unit coupled to the scalar processing unit and configured to provide a vector pipeline datapath employing a vector register for processing a one-dimensional vector quantity. The data processing element further includes an array processing unit coupled to the vector processing unit and configured to provide an array pipeline datapath employing a parallel processing structure for processing a two-dimensional vector quantity. A method of operating a data processing element and a MIMO receiver employing a data processing element are also provided.

## Claims

### Claim 1

A data processing element, comprising:
an input unit configured to provide instructions for scalar, vector and array processing;
a scalar processing unit configured to provide a scalar pipeline datapath for processing a scalar quantity;
a vector processing unit coupled to the scalar processing unit and configured to provide a vector pipeline datapath employing a vector register for processing a one-dimensional vector quantity; and
an array processing unit coupled to the vector processing unit and configured to provide an array pipeline datapath employing a parallel processing structure for processing a two-dimensional vector quantity.

### Claim 2 (depends on 1)

The data processing element as recited in claim 1 wherein the parallel processing structure includes a two-dimensional vector register for processing the two-dimensional vector quantity.

### Claim 3 (depends on 2)

The data processing element as recited in claim 2 wherein a one-dimensional vector quantity can be inserted separately and directly into the two-dimensional register on a row-wise or a column-wise basis.

### Claim 4 (depends on 2)

The data processing element as recited in claim 2 wherein a one-dimensional vector quantity can be extracted separately and directly from the two-dimensional register on a row-wise or a column-wise basis.

### Claim 5 (depends on 1)

The data processing element as recited in claim 1 wherein the parallel processing structure includes a parallel multiplying accumulator for processing the two-dimensional vector quantity.

### Claim 6 (depends on 5)

The data processing element as recited in claim 5 wherein the parallel multiplying accumulator provides a resultant one-dimensional vector quantity.

### Claim 7 (depends on 6)

The data processing element as recited in claim 6 wherein the resultant one-dimensional vector quantity is processed in the vector pipeline datapath.

### Claim 8

A method of operating a data processing element, comprising:
fetching instructions for scalar, vector and array processing;
processing a scalar quantity through a scalar pipeline datapath;
also processing a one-dimensional vector quantity through a vector pipeline datapath employing a vector register; and
further processing a two-dimensional vector quantity through an array pipeline datapath employing a parallel processing structure.

### Claim 9 (depends on 8)

The method as recited in claim 8 wherein the parallel processing structure includes a two-dimensional vector register for processing the two-dimensional vector quantity.

### Claim 10 (depends on 9)

The method as recited in claim 9 wherein a one-dimensional vector quantity can be inserted separately and directly into the two-dimensional register on a row-wise or a column-wise basis.

### Claim 11 (depends on 9)

The method as recited in claim 9 wherein a one-dimensional vector quantity can be extracted separately and directly from the two-dimensional register on a row-wise or a column-wise basis.

### Claim 12 (depends on 8)

The method as recited in claim 8 wherein the parallel processing structure includes a parallel multiplying accumulator for processing the two-dimensional vector quantity.

### Claim 13 (depends on 12)

The method as recited in claim 12 wherein the parallel multiplying accumulator provides a resultant one-dimensional vector quantity.

### Claim 14 (depends on 13)

The method as recited in claim 13 wherein the resultant one-dimensional vector quantity is processed in the vector pipeline datapath.

### Claim 15

a MIMO receiver, comprising:
a MIMO input element, coupled to multiple receive antennas, that provides receive data for scalar, vector and array processing;
a data processing element, including:
an input unit that provides instructions for the scalar, vector and array processing,
a scalar processing unit that provides a scalar pipeline datapath for processing scalar data,
a vector processing unit, coupled to the scalar processing unit, that provides a vector pipeline datapath employing a vector register for processing one-dimensional vector data, and
an array processing unit, coupled to the vector processing unit, that provides an array pipeline datapath having a parallel processing structure for processing two-dimensional vector data; and
a MIMO output element, coupled to the data processing element, that provides an output data stream corresponding to the receive data.

### Claim 16 (depends on 15)

The receiver as recited in claim 15 wherein the parallel processing structure includes a two-dimensional vector register for processing the two-dimensional vector data.

### Claim 17 (depends on 16)

The receiver as recited in claim 16 wherein one-dimensional vector data can be inserted separately and directly into the two-dimensional register on a row-wise or a column-wise basis.

### Claim 18 (depends on 16)

The receiver as recited in claim 16 wherein one-dimensional vector data can be extracted separately and directly from the two-dimensional register on a row-wise or a column-wise basis.

### Claim 19 (depends on 15)

The receiver as recited in claim 15 wherein the parallel processing structure includes a parallel multiplying accumulator for processing the two-dimensional vector data.

### Claim 20 (depends on 19)

The receiver as recited in claim 19 wherein the parallel multiplying accumulator provides resultant one-dimensional vector data.