# US 2013/0159657 A1 · Memory controller with fast reacquisition of read timing to support rank switching

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- Number: US 2013/0159657 A1
- Document ID: US20130159657A1
- Status: Published application
- Kind: A1
- Application number: 13/817,135
- Filed: 2011-08-04
- Published: 2013-06-20
- Earliest claimed: 2010-08-25
- Assignees: Rambus Inc.
- Inventors: Jared L. Zerbe; Ian Shaeffer
- Web page: https://patentgrep.com/patent/US20130159657A1

## CPC

- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G06F 2213/0038: System on Chip
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Techniques for performing fast timing reacquisition of read timing in a memory controller to support rank switching device are described. During operation, a memory controller receives read data for a read operation, wherein the read data includes a calibration preamble. The memory controller uses the calibration preamble to perform a fast timing reacquisition operation to compensate for a timing drift between a clock path and a data path for the read data. In particular, the memory controller performs the fast timing reacquisition by adjusting a data delay line coupled to a clock path associated with a control loop, wherein the control loop controls a data clock which is used to receive read data at the memory controller.

## Claims

### Claim 1

A method for performing a fast timing reacquisition in a memory controller, comprising:
during a read operation,
receiving read data at the memory controller, wherein the read data is preceded by a timing reference signal; and
using the timing reference signal to perform the fast timing reacquisition to compensate for a timing drift between a clock path and a data path for the read data;
wherein performing the fast timing reacquisition comprises adjusting a data delay line coupled to the clock path and associated with a control loop, wherein the control loop controls a clock signal used to receive the read data at the memory controller.

### Claim 2 (depends on 1)

The method of claim 1, wherein the timing reference signal comprises a calibration preamble which is prepended to the read data.

### Claim 3

(canceled)

### Claim 4 (depends on 1)

The method of claim 1, wherein the control loop comprises one of:
a phase-locked loop (PLL); and
a delay-locked loop (DLL).

### Claim 5

(canceled)

### Claim 6

(canceled)

### Claim 7 (depends on 1)

The method of claim 1, wherein performing the fast timing reacquisition comprises performing one of the following operations on a relative phase position to determine the data delay line adjustment:
a binary search;
a parallel search; and
a linear search.

### Claim 8 (depends on 7)

The method of claim 7, wherein performing the binary search involves using a roving sampler with an associated roving-sampler delay line in conjunction with an edge sampler and an associated edge-sampler delay line to perform the binary search.

### Claim 9 (depends on 8)

The method of claim 8, wherein the binary search involves alternately adjusting the edge-sampler delay line and the roving-sampler delay line in increments that decrease by a factor of two to determine a position of a repeating edge transition in the timing reference signal.

### Claim 10 (depends on 8)

The method of claim 8, wherein a given step in the binary search involves:
aggregating multiple samples from the roving sampler and the edge sampler; and
using the aggregated samples to make a binary search decision.

### Claim 11 (depends on 8)

The method of claim 8, wherein the roving sampler and the edge sampler are coupled through respective delay lines to a shared phase mixer.

### Claim 12 (depends on 8)

The method of claim 8, wherein the roving sampler and the edge sampler are coupled through respective delay lines to different phase mixers.

### Claim at position 13

13-18. (canceled)

### Claim 19

A memory controller that facilitates a fast timing reacquisition during a read operation, comprising:
a control loop which controls a clock signal used to receive read data at the memory controller;
a data delay line coupled to a clock path and associated with the control loop; and
fast-locking control logic configured to perform the fast timing reacquisition by,
receiving the read data for the read operation, wherein the read data is preceded by a timing reference signal, and
using the timing reference signal to adjust the data delay line to compensate for a timing drift between the clock path and a data path for the read data.

### Claim 20 (depends on 19)

The memory controller of claim 19, wherein the timing reference signal comprises a calibration preamble which is prepended to the read data.

### Claim 21

(canceled)

### Claim 22 (depends on 19)

The memory controller of claim 19, wherein the control loop comprises one of:
a phase-locked loop (PLL); and
a delay-locked loop (DLL).

### Claim 23

(canceled)

### Claim 24

(canceled)

### Claim 25 (depends on 19)

The memory controller of claim 19, wherein performing the fast timing reacquisition comprises performing one of the following operations on a relative phase position to determine the data delay line adjustment,
a binary search;
a parallel search; and
a linear search.

### Claim 26 (depends on 25)

The memory controller of claim 25, wherein the memory controller further comprises:
a data sampler configured to receive the clock signal through the data delay line;
an edge sampler configured to receive an edge clock signal through an edge-sampler delay line; and
a roving sampler configured to receive a roving clock signal through a roving-sampler delay line;
wherein performing the binary search involves using the data sampler, the edge sampler and the roving sampler to make binary search decisions.

### Claim 27 (depends on 26)

The memory controller of claim 26, wherein the binary search involves alternately adjusting the edge-sampler delay line and the roving-sampler delay line in increments that decrease by a factor of two to determine a position of a repeating edge transition in the timing reference signal.

### Claim 28 (depends on 26)

The memory controller of claim 26, wherein a given step in the binary search involves:
aggregating multiple samples from the roving sampler and the edge sampler; and
using the aggregated samples to make a binary search decision.

### Claim 29 (depends on 26)

The memory controller of claim 26, further comprising a shared phase mixer which is coupled to the roving sampler through the roving-sampler delay line, and to the edge sampler through the edge-sampler delay line.

### Claim 30 (depends on 26)

The memory controller of claim 26, further comprising:
an edge-sampler phase mixer coupled to the edge sampler through the edge-sampler delay line; and
a roving-sampler phase mixer coupled to the roving sampler through the roving-sampler delay line.

### Claim 31

(canceled)

### Claim 32

(canceled)

### Claim 33 (depends on 19)

The memory controller of claim 19, wherein the read operation is a first access to the rank after an idle period for the rank.

### Claim 34 (depends on 33)

The memory controller of claim 33, wherein the read operation is a first access to the rank after a fast rank-switching operation from a preceding rank.

### Claim 35 (depends on 19)

The memory controller of claim 19, wherein the fast rank-switching operation involves looking up a phase for the rank in a table containing phases for each rank in a memory system associated with the memory controller.

### Claim at position 31

36-41. (canceled)