# US 2013/0159653 A1 · Predictive Lock Elision > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159653 A1 - Document ID: US20130159653A1 - Status: Published application - Kind: A1 - Application number: 13/331,221 - Filed: 2011-12-20 - Published: 2013-06-20 - Earliest claimed: 2011-12-20 - Inventors: Martin T. Pohlack; Stephan Diestelhorst - Web page: https://patentgrep.com/patent/US20130159653A1 ## CPC - G06F 9/528: {by using speculative mechanisms} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In at least one embodiment, a method includes determining whether to elide a lock operation based on success of or failure of one or more previous transactional memory operations associated with one or more respective previous lock elisions. In at least one embodiment of the method, the lock operation is associated with a first access of a shared resource and the one or more previous lock elisions are associated with respective one or more previous accesses of the shared resource. ## Claims ### Claim 1 A method comprising: determining whether to elide a lock operation based on success of or failure of one or more previous transactional memory operations associated with one or more respective previous lock elisions. ### Claim 2 (depends on 1) The method as recited in claim 1 wherein the lock operation is associated with a first access of a shared resource and wherein the one or more previous lock elisions are associated with respective one or more previous accesses of the shared resource. ### Claim 3 (depends on 1) The method as recited in claim 1 wherein determining whether to elide the lock operation includes determining a likelihood of success of a transactional memory operation, the likelihood of success based on the success of or failure of the one or more previous transactional memory operations. ### Claim 4 (depends on 3) The method as recited in claim 3 further comprising: determining, based on the likelihood of success, that the transactional memory operation is likely to fail; and attempting the transactional memory operation. ### Claim 5 (depends on 1) The method as recited in claim 1 further comprising: eliding the lock operation; and in response to eliding the lock operation, altering a level of a first state machine, wherein the level of the first state machine indicates a frequency of lock elision attempts relative to lock operations performed. ### Claim 6 (depends on 5) The method as recited in claim 5 wherein the frequency varies exponentially with the level of the first state machine. ### Claim 7 (depends on 5) The method as recited in claim 5 further comprising, after eliding the lock operation and irrespective of the level of the first state machine, eliding a next lock operation. ### Claim 8 (depends on 5) The method as recited in claim 5 further comprising, after eliding the lock operation, performing a predetermined number of subsequent lock operations prior to eliding a subsequent lock operation. ### Claim 9 (depends on 5) The method as recited in claim 5 wherein the first state machine is associated with a first thread of a multithreaded execution, the method further comprising maintaining a second state machine associated with a second thread of the multithreaded execution. ### Claim 10 (depends on 9) The method as recited in claim 9 wherein the first state machine and the second state machine are associated with a resource that is shared by the first thread and the second thread, the method further comprising tracking successes and failures, by the first state machine and the second state machine, of attempted transactional memory operations associated with accesses to the resource. ### Claim 11 An apparatus comprising: a plurality of processing cores comprising at least a first processing core configured to determine whether to elide a lock operation based on success of or failure of one or more previous transactional memory operations associated with one or more respective previous lock elisions. ### Claim 12 (depends on 11) The apparatus as recited in claim 11 wherein the first processing core includes transactional memory logic configured to determine success or failure of transactional memory operations. ### Claim 13 (depends on 11) The apparatus as recited in claim 11 wherein the first processing core is further configured to determine whether to elide the lock operation using instructions executing on the first processing core. ### Claim 14 (depends on 11) The apparatus as recited in claim 11 wherein the first processing core is further configured to alter a level of a state machine in response to success or failure of a transactional memory operation associated with eliding the lock operation. ### Claim 15 (depends on 14) The apparatus as recited in claim 14 wherein the level of the state machine indicates a likelihood of success of eliding the lock operation. ### Claim 16 (depends on 15) The apparatus as recited in claim 15 wherein the likelihood of success varies exponentially with the level of the state machine. ### Claim 17 A non-transitory computer-readable medium encoding instructions to cause a processor to determine whether to elide a lock operation based on success of or failure of one or more previous transactional memory operations associated with one or more respective previous lock elisions. ### Claim 18 (depends on 17) The non-transitory computer-readable medium as recited in claim 17 wherein the instructions are encoded in a shared library. ### Claim 19 (depends on 17) The non-transitory computer-readable medium as recited in claim 17 wherein the instructions further cause the processor to maintain a state machine having a level that indicates a likelihood of success of a transactional memory operation associated with eliding the lock operation. ### Claim 20 (depends on 19) The non-transitory computer-readable medium as recited in claim 19 wherein the likelihood of success varies exponentially with successes and failures of transactional memory operations. ### Claim 21 (depends on 17) The non-transitory computer-readable medium as recited in claim 17 wherein the instructions further cause the processor to maintain a variable that indicates a frequency of lock elision attempts relative to lock operations performed.