# US 2013/0159644 A1 · Data storage device generating redundancy for data path protection of a parity sector

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- Number: US 2013/0159644 A1
- Document ID: US20130159644A1
- Status: Published application
- Kind: A1
- Application number: 13/327,326
- Filed: 2011-12-15
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Western Digital Technologies, Inc.
- Inventors: PATRICK J. LEE
- Web page: https://patentgrep.com/patent/US20130159644A1

## CPC

- G11B 20/1803: {by redundancy in data representation}
- G06F 11/1016: {Error in accessing a memory location, i.e. addressing error}
- G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A data storage device is disclosed comprising a non-volatile memory. A write command is received comprising a first logical block address (LBA) and first user data, and a second LBA and second user data. The first LBA is mapped to a first physical block address (PBA) for addressing a first memory segment. The second LBA is mapped to a second PBA for addressing a second memory segment. First redundancy is generated in response to the first user data, second redundancy in generated in response to the second user data, and parity data is generated in response to the first and second user data. Third redundancy is generated in response to the parity data and in response to at least one of the first LBA and the first PBA and at least one of the second LBA and the second PBA.

## Claims

### Claim 1

A data storage device comprising:
a non-volatile memory comprising a plurality of memory segments; and
control circuitry operable to:
receive a write command comprising a first logical block address (LBA) and first user data, and a second LBA and second user data;
map the first LBA to a first physical block address (PBA) for addressing a first memory segment;
map the second LBA to a second PBA for addressing a second memory segment;
generate first redundancy in response to the first user data;
generate second redundancy in response to the second user data;
generate parity data in response to the first and second user data;
generate third redundancy in response to:
at least one of the first LBA and the first PBA; and
at least one of the second LBA and the second PBA; and
write the first and second user data and parity data to the non-volatile memory and write the first, second, and third redundancy to the non-volatile memory.

### Claim 2 (depends on 1)

The data storage device as recited in claim 1, wherein the control circuitry is operable to:
generate the first redundancy in response to the first user data and at least one of the first LBA and the first PBA; and
generate the second redundancy in response to the second user data and at least one of the second LBA and the second PBA.

### Claim 3 (depends on 2)

The data storage device as recited in claim 2, wherein the control circuitry is operable to generate the third redundancy in response to the first redundancy and the second redundancy.

### Claim 4 (depends on 1)

The data storage device as recited in claim 1, wherein the control circuitry is further operable to:
receive a read command comprising the first and second LBAs;
read the first user data and first redundancy from the non-volatile memory;
correct errors in the first user data using the first redundancy;
read the second user data and second redundancy from the non-volatile memory;
correct errors in the second user data using the second redundancy; and
when the second user data is uncorrectable using the second redundancy:
read the parity data and the third redundancy from the non-volatile memory;
verify the parity data using the third redundancy; and
regenerate the second user data using the first user data and the parity data.

### Claim 5 (depends on 4)

The data storage device as recited in claim 4, wherein the control circuitry is operable to:
generate the first redundancy in response to the first user data and at least one of the first LBA and the first PBA;
generate the second redundancy in response to the second user data and at least one of the second LBA and the second PBA;
correct the first user data in response to the first redundancy and at least one of the first LBA and the first PBA; and
correct the second user data in response to the second redundancy and at least one of the second LBA and the second PBA.

### Claim 6 (depends on 1)

The data storage device as recited in claim 1, wherein the control circuitry is operable to:
combine the first and second LBAs to generate metadata; and
generate the third redundancy in response to the parity data and the metadata.

### Claim 7 (depends on 6)

The data storage device as recited in claim 6, wherein the control circuitry is operable to:
combine the first and second LBAs to regenerate the metadata; and
verify the parity data using the third redundancy and the regenerated metadata.

### Claim 8 (depends on 1)

The data storage device as recited in claim 1, wherein the control circuitry is operable to:
combine the first and second PBAs to generate metadata; and
generate the third redundancy in response to the parity data and the metadata.

### Claim 9 (depends on 8)

The data storage device as recited in claim 8, wherein the control circuitry is operable to:
combine the first and second PBAs to regenerate the metadata; and
verify the parity data using the third redundancy and the regenerated metadata.

### Claim 10 (depends on 1)

The data storage device as recited in claim 1, wherein the control circuitry is operable to generate the third redundancy in response to:
at least one of the first LBA and the first PBA;
at least one of the second LBA and the second PBA; and
at least one of a third LBA and a third PBA for storing the parity data to a third memory segment.

### Claim 11

A method of operating a data storage device comprising a non-volatile memory comprising a plurality of memory segments, the method comprising:
receiving a write command comprising a first logical block address (LBA) and first user data, and a second LBA and second user data;
mapping the first LBA to a first physical block address (PBA) for addressing a first memory segment;
mapping the second LBA to a second PBA for addressing a second memory segment;
generating first redundancy in response to the first user data;
generating second redundancy in response to the second user data;
generating parity data in response to the first and second user data;
generating third redundancy in response to:
at least one of the first LBA and the first PBA; and
at least one of the second LBA and the second PBA; and
writing the first and second user data and parity data to the non-volatile memory and write the first, second, and third redundancy to the non-volatile memory.

### Claim 12 (depends on 11)

The method as recited in claim 11, further comprising:
generating the first redundancy in response to the first user data and at least one of the first LBA and the first PBA; and
generating the second redundancy in response to the second user data and at least one of the second LBA and the second PBA.

### Claim 13 (depends on 12)

The method as recited in claim 12, further comprising generating the third redundancy in response to the first redundancy and the second redundancy.

### Claim 14 (depends on 11)

The method as recited in claim 11, further comprising:
receiving a read command comprising the first and second LBAs;
reading the first user data and first redundancy from the non-volatile memory;
correcting errors in the first user data using the first redundancy;
reading the second user data and second redundancy from the non-volatile memory;
correcting errors in the second user data using the second redundancy; and
when the second user data is uncorrectable using the second redundancy:
reading the parity data and the third redundancy from the non-volatile memory;
verifying the parity data using the third redundancy; and
regenerating the second user data using the first user data and the parity data.

### Claim 15 (depends on 14)

The method as recited in claim 14, further comprising:
generating the first redundancy in response to the first user data and at least one of the first LBA and the first PBA;
generating the second redundancy in response to the second user data and at least one of the second LBA and the second PBA;
correcting the first user data in response to the first redundancy and at least one of the first LBA and the first PBA; and
correcting the second user data in response to the second redundancy and at least one of the second LBA and the second PBA.

### Claim 16 (depends on 11)

The method as recited in claim 11, further comprising:
combining the first and second LBAs to generate metadata; and
generating the third redundancy in response to the parity data and the metadata.

### Claim 17 (depends on 16)

The method as recited in claim 16, further comprising:
combining the first and second LBAs to regenerate the metadata; and
verifying the parity data using the third redundancy and the regenerated metadata.

### Claim 18 (depends on 11)

The method as recited in claim 11, further comprising:
combining the first and second PBAs to generate metadata; and
generating the third redundancy in response to the parity data and the metadata.

### Claim 19 (depends on 18)

The method as recited in claim 18, further comprising:
combining the first and second PBAs to regenerate the metadata; and
verifying the parity data using the third redundancy and the regenerated metadata.

### Claim 20 (depends on 11)

The method as recited in claim 11, further comprising generating the third redundancy in response to:
at least one of the first LBA and the first PBA;
at least one of the second LBA and the second PBA; and
at least one of a third LBA and a third PBA for storing the parity data to a third memory segment.