# US 2013/0159632 A1 · Memory sharing by processors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159632 A1 - Document ID: US20130159632A1 - Status: Published application - Kind: A1 - Application number: 13/707,801 - Filed: 2012-12-07 - Published: 2013-06-20 - Earliest claimed: 2011-12-16 - Assignees: International Business Machines Corporation - Inventors: Victoria Caparros Cabezas; Rik Jongerius; Martin L. Schmatz; Phillip Stanley-Marbell - Web page: https://patentgrep.com/patent/US20130159632A1 ## CPC - G06F 12/0835: {for main memory peripheral accesses (e.g. I/O or DMA)} - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 12/14: Protection against unauthorised use of memory {or access to memory} - G06F 13/1663: {Access to shared memory} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method of memory sharing implemented by logic of a computer memory control unit, the control unit comprising at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N≧2 non-cooperative processors via the second interfaces, the logic operatively coupled to the first and second interfaces. The method includes receiving, via the second interfaces, a request to access data of the main physical memory from a first processor of the set; evaluating if a second processor has previously accessed the data requested by the first processor; and deferring the request from the first processor when the evaluation is positive, or, granting the request from the first processor when the evaluation is negative. ## Claims ### Claim 1 A method of memory sharing implemented by logic of a computer memory control unit, the control unit comprising at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N≧2 non-cooperative processors via the second interfaces, the logic operatively coupled to the first and second interfaces, the method comprising: receiving, via the second interfaces, a request to access data of the main physical memory from a first processor of the set; evaluating if a second processor has previously accessed the data requested by the first processor; and deferring the request from the first processor when the evaluation is positive, or, granting the request from the first processor when the evaluation is negative. ### Claim 2 (depends on 1) The method of claim 1, further comprising: while deferring the request from the first processor, sending a request to the second processor to write back cache lines, that are related to the data requested by the first processor, to the main physical memory. ### Claim 3 (depends on 2) The method of claim 2, wherein sending the request to the second processor is performed via an interrupt pin of the second processor. ### Claim 4 (depends on 3) The method of claim 3, further comprising: while deferring the request from the first processor, and after sending the request to the second processor, ordering the control unit to transmit the requested cache lines, that are received by the control unit from the second processor, to the main physical memory. ### Claim 5 (depends on 4) The method of claim 4, further comprising: once the second processor has written back all requested cache lines to the main physical memory, granting the request from the first processor. ### Claim 6 (depends on 1) The method of claim 1, wherein the evaluation comprises checking in a database of the control unit if a second processor is associated to the data requested by the first processor. ### Claim 7 (depends on 6) The method of claim 6, wherein the method further comprises associating the first processor to the data requested by the first processor in the database. ### Claim 8 (depends on 1) The method of claim 1, wherein the second interfaces are double-data-rate dynamic random access memory interfaces. ### Claim 9 (depends on 1) The method of claim 1, wherein the granularity of management of access is by ranges of physical memory addresses. ### Claim 10 A system, comprising: a computer memory control unit having at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N≧2 non-cooperative processors via the second interfaces; logic operatively coupled to the first and second interfaces, the logic configured to: receive, via the second interfaces, a request to access data of the main physical memory from a first processor of the set; evaluate if a second processor has previously accessed the data requested by the first processor; and defer the request from the first processor when the evaluation is positive, or, granting the request from the first processor when the evaluation is negative. ### Claim 11 (depends on 10) The system of claim 10, wherein the computer memory control unit is connected with the main physical memory via the first interface and with the set of N≧2 non-cooperative processors via the second interfaces. ### Claim 12 A computer readable storage medium having computer readable instructions stored thereon, that when executed by a computer implement a method of memory sharing implemented by logic of a computer memory control unit, the control unit comprising at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N≧2 non-cooperative processors via the second interfaces, the logic operatively coupled to the first and second interfaces, the method comprising: receiving, via the second interfaces, a request to access data of the main physical memory from a first processor of the set; evaluating if a second processor has previously accessed the data requested by the first processor; and deferring the request from the first processor when the evaluation is positive, or, granting the request from the first processor when the evaluation is negative. ### Claim 13 (depends on 12) The computer readable storage medium of claim 12, wherein the method further comprises: while deferring the request from the first processor, sending a request to the second processor to write back cache lines, that are related to the data requested by the first processor, to the main physical memory. ### Claim 14 (depends on 13) The computer readable storage medium of claim 13, wherein sending the request to the second processor is performed via an interrupt pin of the second processor. ### Claim 15 (depends on 14) The computer readable storage medium of claim 14, wherein the method further comprises: while deferring the request from the first processor, and after sending the request to the second processor, ordering the control unit to transmit the requested cache lines, that are received by the control unit from the second processor, to the main physical memory. ### Claim 16 (depends on 15) The computer readable storage medium of claim 15, wherein the method further comprises: once the second processor has written back all requested cache lines to the main physical memory, granting the request from the first processor. ### Claim 17 (depends on 12) The computer readable storage medium of claim 12, wherein the evaluation comprises checking in a database of the control unit if a second processor is associated to the data requested by the first processor. ### Claim 18 (depends on 17) The computer readable storage medium of claim 17, wherein the method further comprises associating the first processor to the data requested by the first processor in the database. ### Claim 19 (depends on 12) The computer readable storage medium of claim 12, wherein the second interfaces are double-data-rate dynamic random access memory interfaces. ### Claim 20 (depends on 12) The computer readable storage medium of claim 12, wherein the granularity of management of access is by ranges of physical memory addresses.