# US 2013/0159628 A1 · Methods and apparatus for source operand collector caching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159628 A1 - Document ID: US20130159628A1 - Status: Published application - Kind: A1 - Application number: 13/326,183 - Filed: 2011-12-14 - Published: 2013-06-20 - Earliest claimed: 2011-12-14 - Assignees: NVIDIA Corporation - Inventors: Jack Hilaire CHOQUETTE; Manuel Olivier Gautho; John Erik Lindholm - Web page: https://patentgrep.com/patent/US20130159628A1 ## CPC - G06F 9/3009: {Thread control instructions} - G06F 9/3012: {Organisation of register space, e.g. banked or distributed register file} - G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods and apparatus for source operand collector caching. In one embodiment, a processor includes a register file that may be coupled to storage elements (i.e., an operand collector) that provide inputs to the datapath of the processor core for executing an instruction. In order to reduce bandwidth between the register file and the operand collector, operands may be cached and reused in subsequent instructions. A scheduling unit maintains a cache table for monitoring which register values are currently stored in the operand collector. The scheduling unit may also configure the operand collector to select the particular storage elements that are coupled to the inputs to the datapath for a given instruction. ## Claims ### Claim 1 A method for executing instructions on a processor core implemented with a source operand collector cache coupled to at least one input of a data path residing within the processor core, the method comprising: decoding an instruction to determine a plurality of operands specified by the instruction; for each operand in the plurality of operands, determining that the operand is not stored in the source operand collector cache, loading the operand into the source operand collector cache from a local register file; and configuring the processor core to execute the instruction across the operands stored in the source operand collector cache. ### Claim 2 (depends on 1) The method of claim 1, further comprising, upon loading the operand into the source operand collector cache, updating a cache table to associate a register index corresponding with the operand with a storage element in the source operand collector cache. ### Claim 3 (depends on 2) The method of claim 2, further comprising: determining that the processor core has written a value to a register in the local register file; and in response to determining that the value has been written to the register, updating the cache table to remove any entries associated with the register. ### Claim 4 (depends on 1) The method of claim 1, wherein the local register file comprises a plurality of register banks. ### Claim 5 (depends on 4) The method of claim 4, further comprising configuring a crossbar to couple a register in a first register bank in the plurality of register banks to a first storage element in the source operand collector cache. ### Claim 6 (depends on 5) The method of claim 5, wherein the crossbar is configured to couple only a single register from each register bank in the plurality of register banks to the source operand collector cache during each clock cycle. ### Claim 7 (depends on 1) The method of claim 1, wherein the source operand collector cache is sized to concurrently store the plurality of operands specified by the instruction and a plurality of operands specified by another decoded instruction. ### Claim 8 A computer-readable storage medium including instructions that, when executed by a processor core implemented with a source operand collector cache coupled to at least one input of a data path residing within the processor core, cause the processor core to perform the steps of: decoding an instruction to determine a plurality of operands specified by the instruction; for each operand in the plurality of operands, determining that the operand is not stored in the source operand collector cache, loading the operand into the source operand collector cache from a local register file; and configuring the processor core to execute the instruction across the operands stored in the source operand collector cache. ### Claim 9 (depends on 8) The computer-readable storage medium of claim 8, the steps further comprising, upon loading the operand into the source operand collector cache, updating a cache table to associate a register index corresponding with the operand with a storage element in the source operand collector cache. ### Claim 10 (depends on 9) The computer-readable storage medium of claim 9, the steps further comprising: determining that the processor core has written a value to a register in the local register file; and in response to determining that the value has been written to the register, updating the cache table to remove any entries associated with the register. ### Claim 11 (depends on 8) The computer-readable storage medium of claim 8, wherein the local register file comprises a plurality of register banks. ### Claim 12 (depends on 11) The computer-readable storage medium of claim 11, the steps further comprising configuring a crossbar to couple a register in a first register bank in the plurality of register banks to a first storage element in the source operand collector cache. ### Claim 13 (depends on 12) The computer-readable storage medium of claim 12, wherein the crossbar is configured to couple only a single register from each register bank in the plurality of register banks to the source operand collector cache during each clock cycle. ### Claim 14 (depends on 8) The computer-readable storage medium of claim 8, wherein the source operand collector cache is sized to concurrently store the plurality of operands specified by the instruction and a plurality of operands specified by another decoded instruction. ### Claim 15 A system comprising: a processor core including a data path for executing instructions; a source operand collector cache coupled to at least one input of the data path; a local register file coupled to the source operand collector cache; and a scheduling unit configured to: decode an instruction to determine a plurality of operands specified by the instruction, for each operand in the plurality of operands, determining that the operand is not stored in the source operand collector cache, load the operand into the source operand collector cache from the local register file, and configure the processor core to execute the instruction across the operands stored in the source operand collector cache. ### Claim 16 (depends on 15) The system of claim 15, further comprising a cache table, and wherein, upon loading the operand into the source operand collector cache, the scheduling unit is further configured to update the cache table to associate a register index corresponding with the operand with a storage element in the source operand collector cache. ### Claim 17 (depends on 15) The system of claim 15, wherein the local register file comprises a plurality of register banks. ### Claim 18 (depends on 17) The system of claim 17, further comprising a crossbar configured to couple a register in a first register bank in the plurality of register banks to a first storage element in the source operand collector cache. ### Claim 19 (depends on 18) The system of claim 18, wherein the crossbar is configured to couple only a single register from each register bank in the plurality of register banks to the source operand collector cache during each clock cycle. ### Claim 20 (depends on 15) The system of claim 15, wherein the source operand collector cache is sized to concurrently store the plurality of operands specified by the instruction and a plurality of operands specified by another decoded instruction.