# US 2013/0159618 A1 · Nearest neighbor serial content addressable memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159618 A1 - Document ID: US20130159618A1 - Status: Published application - Kind: A1 - Application number: 13/765,976 - Filed: 2013-02-13 - Published: 2013-06-20 - Earliest claimed: 2008-07-02 - Inventors: Laurence H. Cooke - Web page: https://patentgrep.com/patent/US20130159618A1 ## CPC - G06F 16/90339: {by using parallel associative memories or content-addressable memories} - G06F 18/22: Matching criteria, e.g. proximity measures - G06F 18/24147: {Distances to closest patterns, e.g. nearest neighbour classification} - G06V 10/955: {using specific electronic processors} - G11C 15/04: using semiconductor elements - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06V: IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs. ## Claims ### Claim 1 A digital logic device comprising: a serial data input to the digital logic device; a plurality of memory circuits; and compare logic circuitry for respective words of a selected one of the plurality of memory circuits; wherein the compare logic circuitry for a respective word of the selected one of the plurality of memory circuits is configured to serially accept each of all bits of the respective word and to serially compare each serially accepted bit from the respective word with a bit of serial data from the serial data input; and wherein the compare logic circuitry is configured to perform the serial comparing for the respective words of the selected one of the plurality of memory circuits in parallel. ### Claim 2 (depends on 1) The digital logic device as in claim 1, wherein said compare logic circuitry includes a shifter/counter to accumulate the comparison results. ### Claim 3 (depends on 1) The digital logic device as in claim 1, wherein the plurality of memory circuits further contains a serial decoder configured to select the selected memory circuit and respective bits of the respective words. ### Claim 4 (depends on 1) The digital logic device as in claim 1, wherein the plurality of memory circuits further contains a decoder configured to address each word of the plurality of memory circuits. ### Claim 5 (depends on 4) The digital logic device as in claim 4, wherein the decoder comprises a serial decoder. ### Claim 6 A digital logic device comprising: a plurality of memories, each containing a plurality of words and logic configured to write data into a respective word of each memory; comparison logic connected to an input and configured to compare the data in multiple words of a selected one of the plurality of memories with data from the input; and encode logic connected to said comparison logic and configured to select a nearest neighbor from the selected one of the plurality of memories, wherein the comparison logic and encode logic are configured to perform a nearest neighbor calculation on a selected one of the plurality of memories while one or more words in an enabled memory, other than the selected one of the plurality of memories, are being written. ### Claim 7 (depends on 6) The digital logic device as in claim 6, wherein the comparison logic is configured to compare the data in all words of the selected one of the plurality of memories with data from the input. ### Claim 8 (depends on 6) The digital logic device as in claim 6, wherein the comparison logic is configured to compare, in parallel, the data in multiple words with the data from the input. ### Claim 9 A method of obtaining from at least one of a plurality of memories a nearest neighbor to a serially-input data word, the method comprising: selecting one of the plurality of memories; comparing, in parallel, data of multiple words of the selected one of the plurality of memories with data from the serially-input data word; and selecting a word of the selected one of the plurality of memories as the nearest neighbor. ### Claim 10 (depends on 9) The method as in claim 9, wherein the comparing and the selecting a word are performed while one or more words are being written in an enabled memory other than the selected one of the plurality of memories. ### Claim 11 (depends on 9) The method as in claim 9, wherein the comparing is performed, in parallel, on all words of the selected one of the plurality of memories. ### Claim 12 A method for finding the location of a minimum of a set of numbers residing in a memory device, each number having a corresponding flag, the method comprising; setting, by a computing device, all of the flags; selecting, by the computing device, an integer m such that a maximum of the set of numbers in the memory device is less than 2m; performing, by the computing device, the following operations until all of the numbers are zero: doubling all of the numbers; clearing a flag corresponding to a number if the number is less than 2m; and subtracting 2m from all of the numbers that are larger than 2m−1; and selecting, by the computing device, and outputting at least one memory location from a set of memory locations corresponding to flags that remain set. ### Claim 13 (depends on 12) The method as in claim 12, wherein the flags are stored in the memory device.