# US 2013/0159610 A1 · Non-volatile semiconductor memory device related method of operation

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- Number: US 2013/0159610 A1
- Document ID: US20130159610A1
- Status: Published application
- Kind: A1
- Application number: 13/711,881
- Filed: 2012-12-12
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Shoichi Kawamura
- Web page: https://patentgrep.com/patent/US20130159610A1

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 11/5621: {using charge storage in a floating gate}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/3468: {Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing}
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A non-volatile semiconductor memory device includes a flash memory including plural blocks of memory cells, and a controller. The controller is configured to program a block of memory cells of the flash memory, to determine a first time period elapsed in which a given percentage of memory cells of the block of memory cells are programmed, and to compare the first time period with a reference second time period. The flash memory and controller are further configured, based on a comparison result between the first time period and the reference time period, to change an operational parameter associated with the block of memory cells, the changed operational parameter being in effect during at a next operational access of the block of memory cells.

## Claims

### Claim 1

A non-volatile semiconductor memory device, comprising:
a flash memory including plural blocks of memory cells;
a controller configured to program a block of memory cells of the flash memory, to determine a first time period elapsed in which a given percentage of memory cells of the block of memory cells are programmed, and to compare the first time period with a reference second time period; and
the flash memory and controller being further configured, based on a comparison result between the first time period and the reference time period, to change an operational parameter associated with the block of memory cells, the changed operational parameter being in effect during at a next operational access of the block of memory cells.

### Claim 2 (depends on 1)

The non-volatile semiconductor memory of claim 1, wherein the operational parameter associated with the block of memory cells is changed when the first time period is less than the reference time period.

### Claim 3 (depends on 1)

The non-volatile semiconductor memory of claim 1, wherein flash memory is responsive to a command received from the controller to change the operational parameter associated with the block of memory cells.

### Claim 4 (depends on 1)

The non-volatile semiconductor memory device of claim 1, wherein the flash memory is configured to output a flag signal when a given percentage N % (where 0<N≦100) of the memory cells of the block are successfully programmed.

### Claim 5 (depends on 4)

The non-volatile semiconductor memory device of claim 4, wherein the controller is configured to determine the first time period based on a time at which the flag signal is output by the flash memory.

### Claim 6 (depends on 1)

The non-volatile semiconductor memory device of claim 1, wherein the controller includes a block address storage to store a block address of the block of memory cells when the first time period is less than the reference time period.

### Claim 7 (depends on 6)

The non-volatile semiconductor memory device of claim 6, wherein, during the next operational access of the block of memory cells, the controller is configured issue a command to change the operational parameter associated with the block of memory cells when the block address is stored in the block address storage.

### Claim 8 (depends on 7)

The non-volatile semiconductor memory device of claim 7, wherein the flash memory is responsive to the command to change the operational parameter associated with the block of memory cells

### Claim 9 (depends on 1)

The non-volatile semiconductor memory device of claim 1, wherein the controller comprises:
a pass time decision unit which determines the first time period, and compares the first time period and the reference time period to determine a correction number of the block indicative of a difference between the first time period and the reference time period;
a block address storage block which stores a block address of the block of memory cells and the correction number of the block of memory cells; and
a condition table which stores a plurality of operational parameters in relation to respective correction numbers.

### Claim 10 (depends on 9)

The non-volatile semiconductor memory of claim 9, wherein the controller is configured, during the next operational access of the block of memory cells, to determine an operational parameter stored in the condition table which corresponds to the correction number stored in the block address storage, and issue a command to the flash memory to change the operational parameter associated with the block of memory cells to the determined operational parameter.

### Claim 11 (depends on 1)

The non-volatile semiconductor memory of claim 1, wherein the operational parameter is at least one of a read voltage, a read verify voltage, a program voltage, an erase voltage and a pass voltage.

### Claim 12 (depends on 11)

The non-volatile semiconductor memory of claim 11, wherein the memory cells are NAND flash memory cells.

### Claim 13 (depends on 1)

The non-volatile semiconductor memory device of claim 1, wherein the block of memory cells is a write-dedicated area of the flash memory in which a same data is programmed into each of the memory cells.

### Claim 14 (depends on 13)

The non-volatile semiconductor memory device of claim 13, wherein data programmed in the write-dedicated area is data written by injecting charges into a floating gate of the memory cells of the block.

### Claim 15

A method of operating a non-volatile semiconductor memory device, the non-volatile semiconductor memory device including a memory controller and a flash memory including plural blocks of memory cells, the method comprising:
programming a block of memory cells of the flash memory;
determining a first time period elapsed in which a given percentage of memory cells of the block of memory cells are programmed;
comparing the first time period with a reference second time period; and
based on a comparison result between the first time period and the reference time period, changing an operational parameter associated with the block of memory cells, the changed operational parameter being in effect during at a next operational access of the block of memory cells.

### Claim 16 (depends on 15)

The method of claim 15, wherein the operational parameter associated with the block of memory cells is changed when the first time period is less than the reference time period.

### Claim 17 (depends on 15)

The method of claim 15, further comprising issuing a command from the controller to the flash memory to change the operational parameter associated with the block of memory cells.

### Claim 18 (depends on 15)

The method of claim 15, outputting a flag signal from the flash memory to the controller when a given percentage N % (where 0<N≦100) of the memory cells of the block are successfully programmed.

### Claim 19 (depends on 15)

The method of claim 15, wherein the operational parameter is at least one of a read voltage, a read verify voltage, a program voltage, an erase voltage and a pass voltage.

### Claim 20 (depends on 19)

The method of claim 19, wherein the memory cells are NAND flash memory cells.