# US 2013/0159602 A1 · Unified memory architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159602 A1 - Document ID: US20130159602A1 - Status: Published application - Kind: A1 - Application number: 13/331,289 - Filed: 2011-12-20 - Published: 2013-06-20 - Earliest claimed: 2011-12-20 - Assignees: BAE Systems Controls Inc. - Inventors: Michael G. Adams; Andrew W. Berner; Mark R. Petrie; Dino A. Gianisis; Andrew F. MacHaffie; James J. Ligas - Web page: https://patentgrep.com/patent/US20130159602A1 ## CPC - G06F 12/02: Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) - G06F 12/0638: {Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70)} - G06F 13/1694: {Configuration of memory controller to different memory types} - G06F 2212/2024: Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Various embodiments of the present invention relate to a Unified Memory Architecture. The Unified Memory Architecture may use MRAM, phase change memory, and/or any other storage having similar features. ## Claims ### Claim 1 A system for providing memory emulation, comprising: a memory element selected from the group consisting of: (a) magnetoresistive random access memory; and (b) phase change memory; and a memory controller in operative communication with the memory element, the memory controller being configured to partition the memory element to include at least a first memory space and a second memory space, the memory controller being configured to cause the first memory space to emulate a volatile memory, the memory controller being configured to cause the second memory space to emulate a non-volatile memory, and the emulation of the non-volatile memory requiring multiple sequential unique writes to perform a memory-related operation. ### Claim 2 (depends on 1) The system of claim 1, wherein the emulated volatile memory is selected from the group comprising: (a) PROM; and (b) RAM. ### Claim 3 (depends on 1) The system of claim 1, wherein the emulated non-volatile memory is FLASH and the memory operation is selected from the group comprising: (a) a program operation; (b) a write to buffer operation; (c) a sector erase operation; and (d) chip erase operation. ### Claim 4 (depends on 1) The system of claim 1, wherein the emulated non-volatile memory is EEPROM and the memory operation is selected from the group comprising: (a) a program operation; and (b) a write to buffer operation. ### Claim 5 (depends on 1) The system of claim 1, wherein the emulated non-volatile memory is NovRAM and the memory operation is selected from the group comprising: (a) a store operation; and (b) a recall operation. ### Claim 6 (depends on 1) The system of claim 1, wherein: the memory controller is configured to cause the first memory space to emulate PROM; the memory controller is configured to partition the memory element to further include at least a third memory space; and the memory controller is configured to cause the third memory space to emulate RAM. ### Claim 7 (depends on 1) The system of claim 1, wherein the memory element comprises a single physical device. ### Claim 8 (depends on 1) The system of claim 1, wherein the memory element comprises a plurality of physical devices. ### Claim 9 (depends on 8) The system of claim 8, wherein the first memory space is on a first one of the plurality of physical devices and the second memory space is on a second one of the plurality of physical devices. ### Claim 10 (depends on 1) The system of claim 1, wherein the memory controller is in operative communication with the memory element via use of a bus. ### Claim 11 (depends on 1) The system of claim 1, wherein the system further comprises a central processing unit and the memory controller is in operative communication with the central processing unit. ### Claim 12 (depends on 1) The system of claim 1, wherein the system further comprises a central processing unit and the memory controller is integrated with the central processing unit. ### Claim 13 (depends on 1) The system of claim 1, wherein the memory element is magnetoresistive random access memory. ### Claim 14 (depends on 1) The system of claim 1, wherein the memory element is phase change memory. ### Claim 15 A method for providing memory emulation with a memory element, comprising: partitioning the memory element to include at least a first memory space and a second memory space; emulating, with the first memory space, a volatile memory; and emulating, with the second memory space, a non-volatile memory; wherein the memory element is selected from the group consisting of: (a) magnetoresistive random access memory; and (b) phase change memory; and wherein the emulation of the non-volatile memory requires multiple sequential unique writes to perform a memory-related operation. ### Claim 16 (depends on 15) The method of claim 15, wherein the emulated volatile memory is selected from the group comprising: (a) PROM; and (b) RAM. ### Claim 17 (depends on 15) The method of claim 15, wherein the emulated non-volatile memory is FLASH and the memory operation is selected from the group comprising: (a) a program operation; (b) a write to buffer operation; (c) a sector erase operation; and (d) chip erase operation. ### Claim 18 (depends on 15) The method of claim 15, wherein the emulated non-volatile memory is EEPROM and the memory operation is selected from the group comprising: (a) a program operation; and (b) a write to buffer operation. ### Claim 19 (depends on 15) The method of claim 15, wherein the emulated non-volatile memory is NovRAM and the memory operation is selected from the group comprising: (a) a store operation; and (b) a recall operation. ### Claim 20 (depends on 15) The method of claim 15, further comprising partitioning the memory element to include at least the first memory space, the second memory space, and a third memory space; wherein the first memory space emulates PROM; and wherein the third memory space emulates RAM. ### Claim 21 (depends on 15) The method of claim 15, wherein: the first memory space has associated therewith, at an initial time, an initial base address and an initial block size; the second memory space has associated therewith, at the initial time, an initial base address and an initial block size; at least one of the first and second memory spaces is remapped, at a time subsequent to the initial time, to have a remapped block size; and the remapped block size is distinct from the initial block size of the respective memory space. ### Claim 22 (depends on 21) The method of claim 21, wherein the first memory space is remapped, at a time subsequent to the initial time, to have a remapped block size and the second memory space is remapped, at a time subsequent to the initial time, to have a remapped block size. ### Claim 23 (depends on 15) The method of claim 15, wherein: the first memory space has associated therewith, at an initial time, an initial base address and an initial size; the second memory space has associated therewith, at the initial time, an initial base address and an initial size; at least one of the first and second memory spaces is remapped, at a time subsequent to the initial time, to have a remapped base address; and the remapped base address is distinct from the initial base address of the respective memory space. ### Claim 24 (depends on 23) The method of claim 23, wherein the first memory space is remapped, at a time subsequent to the initial time, to have a remapped base address and the second memory space is remapped, at a time subsequent to the initial time, to have a remapped base address. ### Claim 25 (depends on 15) The method of claim 15, wherein the memory element is magnetoresistive random access memory. ### Claim 26 (depends on 15) The method of claim 15, wherein the memory element is phase change memory. ### Claim 27 (depends on 15) The method of claim 15, wherein the steps are carried out in the order recited. ### Claim 28 A system for providing memory emulation, comprising: a memory element selected from the group consisting of: (a) magnetoresistive random access memory; and (b) phase change memory; and a memory controller in operative communication with the memory element, the memory controller being configured to partition the memory element to include at least a first memory space, a second memory space, and a third memory space, the memory controller being configured to cause the first memory space to emulate, at an initial time, a PROM configured for read-only access, the memory controller being configured to cause the second memory space to emulate, at the initial time, a non-volatile memory configured for read-only access, the memory controller being configured to cause the third memory space to emulate, at the initial time, a RAM configured for read/write access, and the emulation of the non-volatile memory requiring multiple sequential unique writes to perform a memory-related operation. ### Claim 29 (depends on 28) The system of claim 28, wherein the emulated volatile memory is selected from the group comprising: (a) PROM; and (b) RAM. ### Claim 30 (depends on 28) The system of claim 28, wherein the emulated non-volatile memory is FLASH and the memory operation is selected from the group comprising: (a) a program operation; (b) a write to buffer operation; (c) a sector erase operation; and (d) chip erase operation. ### Claim 31 (depends on 28) The system of claim 28, wherein the emulated non-volatile memory is EEPROM and the memory operation is selected from the group comprising: (a) a program operation; and (b) a write to buffer operation. ### Claim 32 (depends on 28) The system of claim 28, wherein the emulated non-volatile memory is NovRAM and the memory operation is selected from the group comprising: (a) a store operation; and (b) a recall operation. ### Claim 33 (depends on 28) The system of claim 28, wherein the initial time is a time of a power-up of the system. ### Claim 34 (depends on 33) The system of claim 33, wherein at a time subsequent to the initial time at least one of: a base address of the first memory space is changed; a base address of the second memory space is changed; a base address of the third memory space is changed; a block size of the first memory space is changed; a block size of the second memory space is changed; and a block size of the third memory space is changed. ### Claim 35 (depends on 28) The system of claim 28, wherein the memory element is magnetoresistive random access memory. ### Claim 36 (depends on 28) The system of claim 28, wherein the memory element is phase change memory.