# US 2013/0159596 A1 · Techniques for memory de-duplication in a virtual system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159596 A1 - Document ID: US20130159596A1 - Status: Published application - Kind: A1 - Application number: 13/330,398 - Filed: 2011-12-19 - Published: 2013-06-20 - Earliest claimed: 2011-12-19 - Assignees: Intel Corporation - Inventors: Adriaan Van De Ven; Keith Packard - Web page: https://patentgrep.com/patent/US20130159596A1 ## CPC - G06F 12/109: for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) - G06F 2212/152: Virtualized environment, e.g. logically partitioned system - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Techniques for memory de-duplication in a virtual system are described. An apparatus may comprise a first processor circuit coupled to a second processor circuit. A memory unit may be coupled to the first processor circuit and the second processor circuit, the memory unit to store private memory pages and shared memory pages for multiple virtual machines. A memory management application may be operative on the first processor circuit and the second processor circuit in a shared manner to perform memory de-duplication operations on the private memory pages stored in the memory unit to form shared memory pages. The memory management application may perform sequential memory de-duplication operations on the first processor circuit, and parallel memory de-duplication operations on the second processor circuit. Other embodiments are described and claimed. ## Claims ### Claim 1 An apparatus, comprising: a first processor circuit; a second processor circuit coupled to the first processor circuit; a memory unit coupled to the first processor circuit and the second processor circuit, the memory unit to store private memory pages and shared memory pages for multiple virtual machines; and a memory management application operative on the first processor circuit and the second processor circuit to perform memory de-duplication operations on the private memory pages stored in the memory unit to form shared memory pages, the memory management application to perform sequential memory de-duplication operations on the first processor circuit and parallel memory de-duplication operations on the second processor circuit. ### Claim 2 (depends on 1) The apparatus of claim 1, the memory management application comprising: a first set of memory management components operative to perform sequential memory de-duplication operations on the first processor circuit; and a second set of memory management components operative to perform parallel memory de-duplication operations on the second processor circuit. ### Claim 3 (depends on 1) The apparatus of claim 1, the memory management application comprising: a page nomination component operative on the first processor circuit to nominate a set of candidate memory pages suitable for a shared memory page based on a set of selection criteria; a page hash component operative on the second processor circuit to generate one or more page hash values for one or more candidate memory pages within the set of candidate memory pages; a page compare component operative on the second processor circuit to compare the page hash values to identify matching page hash values representing identical memory pages; and a page merge component operative on the first processor circuit to merge the identical memory pages into the shared memory page. ### Claim 4 (depends on 1) The apparatus of claim 1, the memory management application comprising: a page nomination component operative on the first processor circuit to nominate a set of candidate memory pages suitable for a shared memory page based on a set of selection criteria; a page sort component operative on the first processor circuit to sort the candidate memory pages based on a page size for each candidate memory page; a page compare component operative on the second processor circuit to compare the page sizes of adjacent candidate memory pages to identify matching page sizes representing identical memory pages; and a page merge component operative on the first processor circuit to merge the identical memory pages into the shared memory page. ### Claim 5 (depends on 1) The apparatus of claim 1, the first processor circuit comprising a central processing unit (CPU) of a computing platform, and the second processor circuit comprising a graphics processing unit (GPU) of the computing platform. ### Claim 6 (depends on 1) The apparatus of claim 1, comprising a last level cache coupled to the first processor circuit and the second processor circuit. ### Claim 7 (depends on 1) The apparatus of claim 1, comprising a level three cache coupled to the first processor circuit and the second processor circuit. ### Claim 8 (depends on 1) The apparatus of claim 1, comprising a virtualization application operative on the first processor circuit to manage the multiple virtual machines. ### Claim 9 (depends on 1) The apparatus of claim 1, comprising a digital display coupled to the first processor circuit and the second processor circuit, the digital display operative to present information stored in the memory unit. ### Claim 10 A computer-implemented method, comprising: executing, by a first processor circuit, a set of sequential memory de-duplication instructions to convert a set of private memory pages into a shared memory page for multiple virtual machines; and executing, by a second processor circuit, a set of parallel memory de-duplication instructions to convert the set of private memory pages into the shared memory page for the multiple virtual machines. ### Claim 11 (depends on 10) The computer-implemented method of claim 10, comprising retrieving the set of private memory pages, each private memory page stored in a corresponding private memory segment accessible by a single virtual machine. ### Claim 12 (depends on 10) The computer-implemented method of claim 10, comprising storing the shared memory page in a shared memory segment accessible by the multiple virtual machines. ### Claim 13 (depends on 10) The computer-implemented method of claim 10, comprising: nominating, by the first processor circuit, a set of candidate memory pages suitable for the shared memory page based on a set of selection criteria; generating, by the second processor circuit, one or more page hash values for one or more candidate memory pages within the set of candidate memory pages; comparing, by the second processor circuit, the page hash values to identify matching page hash values representing identical memory pages; and merging, by the first processor circuit, the identical memory pages into the shared memory page. ### Claim 14 (depends on 10) The computer-implemented method of claim 10, comprising nominating, by the first processor circuit, a set of candidate memory pages suitable for the shared memory page based on a set of selection criteria; sorting, by the first processor circuit, the candidate memory pages based on a page size for each candidate memory page; comparing, by the second processor circuit, the page sizes of adjacent candidate memory pages to identify matching page sizes representing identical memory pages; and merging, by the first processor circuit, the identical memory pages into the shared memory page. ### Claim 15 (depends on 10) The computer-implemented method of claim 10, comprising communicating information between the first processor circuit and the second processor circuit using a shared level three cache. ### Claim 16 At least one computer-readable storage medium comprising instructions that, when executed, cause a system to: perform, by a first processor circuit, a set of sequential memory de-duplication operations to convert multiple private memory pages for multiple virtual machines into a shared memory page for the multiple virtual machines; and perform, by a second processor circuit, a set of parallel memory de-duplication operations to convert the multiple private memory pages for the multiple virtual machines into the shared memory page for the virtual machines. ### Claim 17 (depends on 16) The computer-readable storage medium of claim 16, comprising instructions that when executed cause the system to: retrieve the multiple private memory pages from corresponding private memory segments accessible by each of the virtual machines; and store the shared memory page in a shared memory segment accessible by the multiple virtual machines. ### Claim 18 (depends on 16) The computer-readable storage medium of claim 16, comprising instructions that when executed cause the system to: nominate, by the first processor circuit, a set of candidate memory pages suitable for the shared memory page based on a set of selection criteria; generate, by the second processor circuit, one or more page hash values for one or more candidate memory pages within the set of candidate memory pages; compare, by the second processor circuit, the page hash values to identify matching page hash values representing identical memory pages; and merge, by the first processor circuit, the identical memory pages into the shared memory page. ### Claim 19 (depends on 16) The computer-readable storage medium of claim 16, comprising instructions that when executed cause the system to: nominate, by the first processor circuit, a set of candidate memory pages suitable for the shared memory page based on a set of selection criteria; sort, by the first processor circuit, the candidate memory pages based on a page size for each candidate memory page; compare, by the second processor circuit, the page sizes of adjacent candidate memory pages to identify matching page sizes representing identical memory pages; and merge, by the first processor circuit, the identical memory pages into the shared memory page. ### Claim 20 (depends on 16) The computer-readable storage medium of claim 16, comprising instructions that when executed cause the system to communicate information between the first processor circuit and the second processor circuit using a shared level three cache.