# US 2013/0159592 A1 · Accessing A Logic Device Through A Serial Interface > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0159592 A1 - Document ID: US20130159592A1 - Status: Published application - Kind: A1 - Application number: 13/325,432 - Filed: 2011-12-14 - Published: 2013-06-20 - Earliest claimed: 2011-12-14 - Assignees: International Business Machines Corporation - Inventors: Alfredo Aldereguia; James J. Parsonese; Grace A. Richter; Christopher L. Wood - Web page: https://patentgrep.com/patent/US20130159592A1 ## CPC - G06F 12/02: Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) - H03K 19/173: using elementary logic circuits as components - G06F 2212/206: Memory mapped I/O - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Methods, apparatuses, and computer program products for accessing a logic device through a serial interface are provided. Embodiments include receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding to a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request. Embodiments also include identifying in the non-linear address mode a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request. ## Claims ### Claim 1 A method of accessing a logic device through a serial interface, the logic device including a plurality of registers, the method comprising: receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding to a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request; identifying in the non-linear address mode, by the logic device, a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request. ### Claim 2 (depends on 1) The method of claim 1 further comprising: receiving, by the logic device, a second data access request indicating a linear address mode, wherein the second data access request includes a linear address corresponding to a linear index specifying a plurality of linear addresses, the linear index sequentially associating each linear address with a specific location with the logic device; performing at the linear address, by the logic device, a serial transaction in accordance with the second data access request. ### Claim 3 (depends on 2) The method of claim 2 wherein the plurality of registers include a first set of registers addressed in accordance with the non-linear address mode and a second set of registers addressed in accordance with the linear address mode. ### Claim 4 (depends on 1) The method of claim 1 further comprising: receiving, by the logic device, a particular data access request that includes an address mode value; selecting based on the address mode value, by the logic device, one of the linear address mode and the non-linear address mode for processing of the particular data access request; and processing, by the logic device, the particular data access request in accordance with the selection of one of the non-linear address mode and the linear address mode. ### Claim 5 (depends on 1) The method of claim 1 wherein the first data access request includes an ending page offset for the performance of the first data access request. ### Claim 6 (depends on 1) The method of claim 1 wherein the logic device is a programmable logic device. ### Claim 7 An apparatus for accessing a logic device through a serial interface, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that when executed by the computer processor cause the apparatus to carry out the steps of: receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request; identifying in the non-linear address mode, by the logic device, a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request. ### Claim 8 (depends on 7) The apparatus of claim 7 further comprising computer program instructions that when executed by the computer processor cause the apparatus to carry out the steps of: receiving, by the logic device, a second data access request indicating a linear address mode, wherein the second data access request includes a linear address corresponding to a linear index specifying a plurality of linear addresses, the linear index sequentially associating each linear address with a specific location with the logic device; performing at the linear address, by the logic device, a serial transaction in accordance with the second data access request. ### Claim 9 (depends on 8) The apparatus of claim 8 wherein the plurality of registers include a first set of registers addressed in accordance with the non-linear address mode and a second set of registers addressed in accordance with the linear address mode. ### Claim 10 (depends on 7) The apparatus of claim 7 further comprising computer program instructions that when executed by the computer processor cause the apparatus to carry out the steps of: receiving, by the logic device, a particular data access request that includes an address mode value; selecting based on the address mode value, by the logic device, one of the linear address mode and the non-linear address mode for processing of the particular data access request; and processing, by the logic device, the particular data access request in accordance with the selection of one of the non-linear address mode and the linear address mode. ### Claim 11 (depends on 7) The apparatus of claim 7 wherein the first data access request includes an ending page offset for the performance of the first data access request. ### Claim 12 (depends on 7) The apparatus of claim 7 wherein the logic device is a programmable logic device. ### Claim 13 A computer program product for accessing a logic device through a serial interface, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions capable, when executed, of causing a computer to carry out the steps of: receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request; identifying in the non-linear address mode, by the logic device, a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request. ### Claim 14 (depends on 13) The computer program product of claim 13 further comprising computer program instructions capable, when executed, of causing a computer to carry out the steps of: receiving, by the logic device, a second data access request indicating a linear address mode, wherein the second data access request includes a linear address corresponding to a linear index specifying a plurality of linear addresses, the linear index sequentially associating each linear address with a specific location with the logic device; performing at the linear address, by the logic device, a serial transaction in accordance with the second data access request. ### Claim 15 (depends on 14) The computer program product of claim 14 wherein the plurality of registers include a first set of registers addressed in accordance with the non-linear address mode and a second set of registers addressed in accordance with the linear address mode. ### Claim 16 (depends on 13) The computer program product of claim 13 further comprising computer program instructions capable, when executed, of causing a computer to carry out the steps of: receiving, by the logic device, a particular data access request that includes an address mode value; selecting based on the address mode value, by the logic device, one of the linear address mode and the non-linear address mode for processing of the particular data access request; and processing, by the logic device, the particular data access request in accordance with the selection of one of the non-linear address mode and the linear address mode. ### Claim 17 (depends on 13) The computer program product of claim 13 wherein the first data access request includes an ending page offset for the performance of the first data access request. ### Claim 18 (depends on 13) The computer program product of claim 13 wherein the logic device is a programmable logic device. ### Claim 19 A method of accessing a logic device through a serial interface, the logic device including a plurality of registers, the method comprising: transmitting to the serial interface of the logic device, by a processing device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding to a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request; receiving from the serial interface of the logic device, by the processing device, an indication that the logic device performed the first data access request at a location identified by the non-linear address and the starting page. ### Claim 20 (depends on 19) The method of claim 19 further comprising: transmitting to the logic device, by the processing device, a second data access request indicating a linear address mode, wherein the second data access request includes a linear address corresponding to a linear index specifying a plurality of linear addresses, the linear index sequentially associating each linear address with a specific location with the logic device; and receiving from the logic device, by the processing device, an indication that the logic device performed the second data access request at the linear address.