# US 2013/0158973 A1 · Parity error detection verification > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0158973 A1 - Document ID: US20130158973A1 - Status: Published application - Kind: A1 - Application number: 13/331,172 - Filed: 2011-12-20 - Published: 2013-06-20 - Earliest claimed: 2011-12-20 - Assignees: Advanced Micro Devices, Inc. - Inventors: Christopher E. Hsiong - Web page: https://patentgrep.com/patent/US20130158973A1 ## CPC - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F 2117/02: Fault tolerance, e.g. for transient fault suppression - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A circuit design is simulated on a computing system. Simulating the circuit design includes selecting a first memory location in the circuit design in which to introduce a parity error according to the first memory location having a higher probability of being read than a second memory location of the circuit design. A parity error is inserted in the first memory location during simulation of the design. ## Claims ### Claim 1 A method of simulating a circuit design on a computing system comprising: selecting a first memory location in the circuit design in which to introduce a parity error according to the first memory location having a higher probability of being read than a second memory location of the circuit design; and inserting the parity error in the first memory location during simulation of the circuit design. ### Claim 2 (depends on 1) The method as recited in claim 1 further comprising determining, using error detection logic of the circuit design during simulation, that the first memory location is associated with the parity error. ### Claim 3 (depends on 1) The method as recited in claim 1 wherein the circuit design is represented in hardware description language (HDL). ### Claim 4 (depends on 1) The method as recited in claim 1 wherein the first memory location is in a first-in first-out (FIFO) buffer, and wherein a head pointer of the FIFO buffer indicates the first memory location as next to be read from the FIFO buffer. ### Claim 5 (depends on 4) The method as recited in claim 4 wherein the FIFO buffer is an in-order FIFO buffer, the method further comprising introducing a parity error into a third memory location of the FIFO buffer, wherein the third memory location is adjacent to the first memory location. ### Claim 6 (depends on 1) The method as recited in claim 1 wherein first memory location is part of an array of memory locations each associated with a corresponding valid bit, and wherein the first memory location is one of the memory locations of the out-of-order array indicated to be valid. ### Claim 7 (depends on 6) The method as recited in claim 6 wherein the second memory location is one of the memory locations of the array indicated to be invalid. ### Claim 8 (depends on 1) The method as recited in claim 1 wherein the first memory location is a register of a register file, and wherein the circuit design further includes a list indicating registers of the register file, the first memory location not indicated by the list. ### Claim 9 (depends on 8) The method as recited in claim 8 wherein the list indicates those registers of the register file that have not been written to or are obsolete and unused. ### Claim 10 (depends on 8) The method as recited in claim 8 wherein the second memory location is a register of the register file and is indicated by the list. ### Claim 11 (depends on 1) The method as recited in claim 1 wherein the first memory location is a register of a register file, the register associated with a corresponding architectural register. ### Claim 12 A non-transitory computer-readable storage medium encoding instructions executable by a computing system to cause the computing system to: determine that a first memory location of a circuit design is associated with a higher probability of being read than a second memory location of the circuit design; and cause a parity error associated with the first memory location during simulation of the circuit design. ### Claim 13 (depends on 12) The non-transitory computer-readable storage medium as recited in claim 12 wherein the circuit design is represented in hardware description language (HDL). ### Claim 14 (depends on 12) The non-transitory computer-readable storage medium as recited in claim 12 wherein the circuit design includes error detection logic to perform a parity check on data associated with the first memory location. ### Claim 15 (depends on 12) The non-transitory computer-readable storage medium as recited in claim 12 wherein the circuit design includes a first-in first-out (FIFO) buffer that includes the first memory location, and wherein a head pointer of the FIFO buffer indicates the first memory location as next to be read from the FIFO buffer. ### Claim 16 (depends on 12) The non-transitory computer-readable storage medium as recited in claim 12 wherein the circuit design includes an array of memory locations each associated with a corresponding valid bit, and wherein the first memory location is one of the memory locations of the array indicated to be valid. ### Claim 17 (depends on 12) The non-transitory computer-readable storage medium as recited in claim 12 wherein the circuit design includes a register file, wherein the second memory location is a register of the register file, and wherein the circuit design further includes a list indicating registers of the register file that have not been written to or are obsolete and unused, the second memory location indicated by the list. ### Claim 18 (depends on 12) The non-transitory computer-readable storage medium as recited in claim 12 wherein the circuit design includes a register file including the first memory location, and wherein the first memory location is a physical register of the register file, the physical register associated with a corresponding architectural register. ### Claim 19 A method of simulating a circuit design on a computing system, the method comprising: in response to a register of a register file being included in an architectural-to-physical register mapping of a simulation of the circuit design, introducing a parity error associated with the register in the simulation. ### Claim 20 (depends on 19) The method as recited in claim 19 wherein the architectural-to-physical register mapping indicates a correspondence of architectural registers to respective physical registers of the register file.