# US 2013/0158905 A1 · Test apparatus and test method

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- Number: US 2013/0158905 A1
- Document ID: US20130158905A1
- Status: Published application
- Kind: A1
- Application number: 13/734,211
- Filed: 2013-01-04
- Published: 2013-06-20
- Earliest claimed: 2010-07-07
- Assignees: Advantest Corporation
- Inventors: Masaru Tsuto
- Web page: https://patentgrep.com/patent/US20130158905A1

## CPC

- G06F 17/00: Digital computing or data processing equipment or methods, specially adapted for specific functions (information retrieval, database structures or file system structures therefor G06F16/00)
- G01R 31/2601: {Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence)}
- G01R 31/31908: {Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns}
- G01R 31/31726: {Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A synchronization pattern generating unit generates a synchronization pattern required for a clock recovery unit which has been built into a DUT to maintain a link with an external circuit. A gate signal generating unit generates a gate signal which is asserted in a period in which a vector pattern is to be supplied to the DUT. In a first mode, a pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs a fixed output level during a period in which the gate signal is negated. In a second mode, the pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs the synchronization pattern during a period in which the gate signal is negated.

## Claims

### Claim 1

A test apparatus comprising:
a vector pattern generating unit configured to generate a vector pattern which specifies a vector of a device under test;
a synchronization pattern generating unit configured to generate a synchronization pattern required for a clock recovery unit which has been built into the device under test to maintain a link with an external circuit;
a gate signal generating unit configured to generate a gate signal which is asserted during a period of time in which the vector pattern is to be supplied to the device under test; and
a pattern selecting unit configured to receive the vector pattern, the synchronization pattern, and a control signal which specifies a mode, and to operate such that, in a first mode, it outputs the vector pattern during a period of time in which the gate signal is asserted and outputs a fixed output level during a period of time in which the gate signal is negated, and such that, in a second mode, it outputs the vector pattern during a period of time in which the gate signal is asserted and outputs the synchronization pattern during a period of time in which the gate signal is negated.

### Claim 2 (depends on 1)

A test apparatus according to claim 1, further comprising a clock signal generating unit configured to generate a clock signal,
wherein the pattern selecting unit is configured such that, in a third mode, it outputs the clock signal regardless of the level of the gate signal.

### Claim 3

A test method for supplying a signal to a device under test, the test method comprising:
generating a vector pattern which specifies a vector of a device under test;
generating a synchronization pattern required for a clock recovery unit which has been built into the device under test to maintain a link with an external circuit;
generating a gate signal which is asserted during a period of time in which the vector pattern is to be supplied to the device under test;
selecting a mode;
in a first mode, outputting the vector pattern during a period of time in which the gate signal is asserted, and outputting a fixed output level during a period of time in which the gate signal is negated; and
in a second mode, outputting the vector pattern during a period of time in which the gate signal is asserted, and outputting the synchronization pattern during a period of time in which the gate signal is negated.

### Claim 4 (depends on 3)

A test method according to claim 3, further comprising:
generating a clock signal; and
in a third mode, outputting the clock signal regardless of the level of the gate signal.