# US 2013/0157482 A1 · Decoupling arrangement

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- Number: US 2013/0157482 A1
- Document ID: US20130157482A1
- Status: Published application
- Kind: A1
- Application number: 13/331,500
- Filed: 2011-12-20
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: Intel Corporation
- Inventors: William L. Barber; Keith Pinson; Andrew P. Collins; Boping Wu; Isaac Ali; Colin L. Perry
- Web page: https://patentgrep.com/patent/US20130157482A1

## CPC

- H05K 1/0231: {Capacitors or dielectric substances}
- H02H 9/04: responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T)
- H05K 1/025: {Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance (H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H10W44/20)}
- H10W 72/00: Interconnections or connectors in packages
- H05K 2201/09672: Superposed layout, i.e. in different planes
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

## Claims

### Claim 1

An apparatus, comprising:
a decoupling arrangement operative to reduce series inductance between an input port and a decoupling component, the decoupling arrangement comprising:
an input current path electrically coupling the input port to the decoupling component; and
a return current path electrically coupling the input port to the decoupling component, the input current path and the return current path spaced apart and positioned substantially atop one another.

### Claim 2 (depends on 1)

The apparatus of claim 1, the input current path comprising an electrically conductive trace.

### Claim 3 (depends on 1)

The apparatus of claim 1, the return current path comprising an electrically conductive trace.

### Claim 4 (depends on 1)

The apparatus of claim 1, the decoupling component comprising a capacitor.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the input port is integrated within a system on a chip (SoC) device.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the input port is integrated within a multi-chip module (MCM) device.

### Claim 7 (depends on 1)

The apparatus of claim 1, in which the input port is integrated within a printed circuit board (PCB).

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the input port is a power supply port.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the input port is a high speed switching port.

### Claim 10

An apparatus, comprising:
a decoupling arrangement operative to reduce series inductance between an input port and a decoupling component, the decoupling arrangement comprising:
a first input current path electrically coupling the input port to the decoupling component, the first input current path in a first plane;
a second input current path electrically coupling the input port to the decoupling component, the second input current path in a second plane spaced apart from and parallel to the first plane;
a first return current path electrically coupling the input port to the decoupling component, the first return current path in the first plane;
a second return current path electrically coupling the input port to the decoupling component, the second return current path in the second plane;
the first input current path and the second return current path positioned substantially atop one another; and
the second input current path and the first return current path positioned substantially atop one another.

### Claim 11 (depends on 10)

The apparatus of claim 10, the first and second input current paths and the first and second return current paths comprising electrically conductive traces.

### Claim 12 (depends on 10)

The apparatus of claim 10, the decoupling component comprising a capacitor.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the input port is integrated within one of a system on a chip (SoC) device and multi-chip module (MCM) device.

### Claim 14 (depends on 10)

The apparatus of claim 10, in which the input port is integrated within a printed circuit board (PCB).

### Claim 15 (depends on 10)

The apparatus of claim 10, wherein the input port is one of a power supply port, reference port, and high speed switching port.

### Claim 16

An apparatus, comprising:
a decoupling arrangement operative to reduce series inductance between an input port and a decoupling component, the decoupling arrangement comprising:
a matrix of interleaved input current paths and return current paths, each of the interleaved input current paths and return current paths coupling the input port to the decoupling component, the matrix arranged in rows and columns such that:
each row defines a separate plane wherein adjacent columns within each row alternate between an input current path and a return current path; and
the first column in each row alternates between an input current path and a return current path.

### Claim 17 (depends on 16)

The apparatus of claim 16, the input current paths and the return current paths comprising electrically conductive traces.

### Claim 18 (depends on 16)

The apparatus of claim 16, the decoupling component comprising a capacitor.

### Claim 19 (depends on 16)

The apparatus of claim 16, wherein the input port is integrated within one of a system on a chip (SoC) device and multi-chip module (MCM) device.

### Claim 20 (depends on 16)

The apparatus of claim 16, in which the input port is integrated within a printed circuit board (PCB).

### Claim 21 (depends on 16)

The apparatus of claim 16, wherein the input port is one of a power supply port, reference port, and high speed switching port.

### Claim 22

A system, comprising:
a printed circuit board (PCB);
a chip component including an input port, the chip component mounted on the PCB;
a decoupling component mounted on the PCB; and
a decoupling arrangement operative to reduce series inductance between the input port and the decoupling component.

### Claim 23 (depends on 22)

The system of claim 22, the chip component comprising a system on a chip (SoC).

### Claim 24 (depends on 22)

The system of claim 22, the chip component comprising a multi-chip module (MCM).

### Claim 25 (depends on 22)

The system of claim 22, the decoupling arrangement comprising:
an input current path electrically coupling the input port to the decoupling component; and
a return current path electrically coupling the input port to the decoupling component, the input current path and the return current path spaced apart and positioned substantially atop one another.

### Claim 26 (depends on 22)

The system of claim 22, the decoupling arrangement comprising:
a first input current path electrically coupling the input port to the decoupling component, the first input current path in a first plane;
a second input current path electrically coupling the input port to the decoupling component, the second input current path in a second plane spaced apart from and parallel to the first plane;
a first return current path electrically coupling the input port to the decoupling component, the first return current path in the first plane;
a second return current path electrically coupling the input port to the decoupling component, the second return current path in the second plane;
the first input current path and the second return current path positioned substantially atop one another; and
the second input current path and the first return current path positioned substantially atop one another.

### Claim 27 (depends on 22)

The system of claim 22, the decoupling arrangement comprising:
a matrix of interleaved input current paths and return current paths, each of the interleaved input current paths and return current paths coupling the input port to the decoupling component, the matrix arranged in rows and columns such that:
each row defines a separate plane wherein adjacent columns within each row alternate between an input current path and a return current path; and
the first column in each row alternates between an input current path and a return current path.