# US 2013/0157461 A1 · Method for fabricating semiconductor memory device

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- Number: US 2013/0157461 A1
- Document ID: US20130157461A1
- Status: Published application
- Kind: A1
- Application number: 13/478,625
- Filed: 2012-05-23
- Published: 2013-06-20
- Earliest claimed: 2011-12-19
- Assignees: Hynix Semiconductor Inc.
- Inventors: Won-Kyu KIM
- Web page: https://patentgrep.com/patent/US20130157461A1

## CPC

- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for fabricating a semiconductor device includes forming an etch-target layer over a substrate having a first region and a second region, stacking first and second hard mask layers over the etch-target layer, forming spacer patterns over the second hard mask layer of the first area, etching the second hard mask layer using the spacer patterns as an etch barrier, forming a hard mask pattern over the first hard mask layer of the second region, etching the first hard mask layer using the second hard mask layer of the first region and the hard mask pattern of the second region as etch barriers, removing the hard mask pattern of the second region, and etching the etch-target layer using the first and second hard mask layers of the first region and the first hard mask layer of the second region as etch barriers.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
forming an etch-target layer over a substrate having a first region and a second region;
stacking a first hard mask layer and a second hard mask layer over the etch-target layer, the second hard mask layer having an etching selectivity with the first hard mask layer;
forming spacer patterns over the second hard mask layer of the first region;
etching the second hard mask layer using the spacer patterns as an etch barrier;
forming a hard mask pattern over the first hard mask layer of the second region;
etching the first hard mask layer using the second hard mask layer of the first region and the hard mask pattern of the second region as etch barriers;
removing the hard mask pattern of the second region; and
etching the etch-target layer using the first and second hard mask layers of the first region and the first hard mask layer of the second region as etch barriers.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming of the spacer patterns comprises:
forming a sacrificial pattern over the second hard mask layer of the first region;
forming an oxide layer along the entire surface of a structure including the sacrificial pattern;
forming the spacer patterns on the sidewalls of the sacrificial pattern by etching the oxide layer; and
removing the sacrificial pattern.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming of the hard mask pattern comprises:
forming a hard mask carbon layer over the first hard mask layer;
forming a photoresist pattern over the hard mask carbon layer of the second region; and
etching the hard mask carbon layer using the photoresist pattern as an etch barrier.

### Claim 4 (depends on 2)

The method of claim 2, wherein the sacrificial pattern comprises amorphous carbon or spin-on carbon (SOC).

### Claim 5 (depends on 1)

The method of claim 1, wherein the hard mask pattern comprises amorphous carbon or spin-on carbon (SOC).

### Claim 6 (depends on 1)

The method of claim 1, wherein the removing of the hard mask pattern is performed by dry etching.

### Claim 7 (depends on 6)

The method of claim 6, wherein the dry etching comprises an oxygen strip process.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first hard mask layer comprises nitride, and the second hard mask layer comprises polysilicon.

### Claim 9 (depends on 1)

The method of claim 1, wherein the etch-target layer comprises a conductive layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein the etch-target layer comprises a stacked structure of a barrier metal layer and a metal layer.

### Claim 11 (depends on 1)

The method of claim 1, wherein the first region comprises a cell region, and the second region comprises a peripheral region.

### Claim 12

A method for fabricating a semiconductor device, comprising:
forming an etch-target layer over a substrate having a first region and a second region;
forming a first hard mask pattern and a second hard mask pattern in the first region and the second region, respectively, wherein the first and second hard mask patterns have different heights; and
performing an etching process using the first and second hard mask patterns as an etch barrier to form a first pattern and a second pattern in the first region and the second region, respectively.

### Claim 13 (depends on 12)

The method of claim 12, wherein the forming of the first and second hard mask patterns comprises:
stacking a first hard mask layer and a second hard mask layer over the etch-target layer, the second hard mask layer having an etching selectivity with the first hard mask layer;
forming the second hard mask pattern of the first region by removing the second hard mask layer of the second region;
forming a hard mask carbon pattern;
forming the first hard mask pattern of the first and second regions using the second hard mask pattern and the hard mask carbon pattern as etch barriers; and
removing the hard mask carbon pattern.

### Claim 14 (depends on 13)

The method of claim 13, wherein the forming of the second hard mask pattern of the first region comprises:
forming spacer patterns over the second hard mask layer of the first region; and
etching the second hard mask layer using the spacer patterns as an etch barrier to remove the second hard mask layer of the second region.

### Claim 15 (depends on 13)

The method of claim 13, wherein the forming of the hard mask carbon pattern comprises:
forming a hard mask carbon layer to fill spaces between the second hard mask pattern over a structure including the first hard mask layer;
forming a photoresist pattern over the hard mask carbon layer of the second region; and
etching the hard mask carbon layer using the photoresist pattern as an etch barrier to form the hard mask carbon pattern.