# US 2013/0157457 A1 · Interconnects for stacked non-volatile memory device and method

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- Number: US 2013/0157457 A1
- Document ID: US20130157457A1
- Status: Published application
- Kind: A1
- Application number: 13/764,698
- Filed: 2013-02-11
- Published: 2013-06-20
- Earliest claimed: 2010-11-04
- Assignees: Crossbar, Inc.
- Inventors: Scott Brad HERNER
- Web page: https://patentgrep.com/patent/US20130157457A1

## CPC

- H10W 20/0698: {Local interconnections}
- H10W 20/42: Vias, e.g. via plugs
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure.

## Claims

### Claim 1

A method of forming a memory device; comprising:
providing a substrate having a surface region;
forming a first dielectric material overlying the surface region of the semiconductor substrate;
defining a cell region, a first peripheral region, and a second peripheral region;
forming a first crossbar array of memory cells in the cell region overlying the first dielectric material; the first crossbar array of memory cells comprises a first bottom wiring structure spatially extending in a first direction and including a portion extending into the first peripheral region, a first top wiring structure spatially extending in a second direction perpendicular to the first direction and a first switching region sandwiched in an intersection region between the first top wiring structure and the first bottom wiring structure, the first top wiring structure including a portion extending into the second peripheral region;
forming a second dielectric material overlying the first crossbar array of memory cells;
forming a via opening in a portion of the first periphery region, the via opening exposing a portion of the first bottom wiring structure and a portion of the substrate;
depositing a second bottom wiring material to fill the via opening and to form a thickness of second bottom wiring material overlying the second dielectric material;
subjecting the second bottom wiring material to a pattern and etch process to form a second bottom wiring structure for a second array of memory cells, the second bottom wiring structure including a portion spatially extending parallel to the first bottom wiring structure in the cell region and a via structure in the first peripheral region, the via structure electrically connecting the second bottom wiring structure and the first bottom wiring structure to a first control circuitry on the substrate.