# US 2013/0157455 A1 · Electrical Contact Alignment Posts

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- Number: US 2013/0157455 A1
- Document ID: US20130157455A1
- Status: Published application
- Kind: A1
- Application number: 13/765,280
- Filed: 2013-02-12
- Published: 2013-06-20
- Earliest claimed: 2010-08-04
- Assignees: International Buiness Machines Corporation
- Inventors: David Justin West; David John Russell
- Web page: https://patentgrep.com/patent/US20130157455A1

## CPC

- H10P 14/40: of conductive or resistive materials
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 46/301: {for alignment}
- H10W 46/601: {for use after dicing}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/072: {of bump connectors}
- H10W 72/07227: {involving guiding structures, e.g. spacers or supporting members}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

## Claims

### Claim 1

(canceled)

### Claim 2

(canceled)

### Claim 3

(canceled)

### Claim 4

(canceled)

### Claim 5

(canceled)

### Claim 6

A method for assembling a first plurality of integrated circuit pads upon a surface of an integrated circuit with a corresponding first plurality of pads upon a surface of a substrate, the method comprising the steps of:
(a) forming a first plurality of alignment posts terminating with dome shaped solder on the integrated circuit surface;
(b) forming a second plurality of alignment posts terminating with dome shaped solder on the substrate surface and each substrate alignment post located to be positioned against at least one of the integrated circuit alignment posts upon assembly;
(c) positioning the integrated circuit pads to contact the substrate pads wherein at least one of the integrated circuit alignment posts is positioned adjacent to at least one of the substrate alignment posts.

### Claim 7 (depends on 6)

A method according to claim 6 wherein the integrated circuit alignment posts are formed to be of greater height from the integrated circuit surface than the integrated circuit pads.

### Claim 8 (depends on 6)

A method according to claim 6 wherein the substrate alignment posts are formed to be of greater height from the substrate surface than the substrate pads.

### Claim 9

(canceled)

### Claim 10 (depends on 6)

A method according to claim 6 wherein the interconnection pads of at least one of the electronic devices include solder upon the pads.

### Claim 11 (depends on 6)

A method according to claim 6 wherein the integrated circuit alignment posts and substrate alignment posts are located upon their respective surfaces to prevent lateral motion between the integrated circuit and substrate after assembly.

### Claim 12

(canceled)

### Claim 13

(canceled)

### Claim 14

(canceled)

### Claim 15

(canceled)

### Claim 16

(canceled)

### Claim 17

(canceled)

### Claim 18 (depends on 6)

The method according to claim 6 wherein the step of forming the first plurality of alignment posts includes locating the alignment posts adjacent to the first plurality of integrated circuit pads.