# US 2013/0157449 A1 · Method for forming metal gate

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- Number: US 2013/0157449 A1
- Document ID: US20130157449A1
- Status: Published application
- Kind: A1
- Application number: 13/686,483
- Filed: 2012-11-27
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Semiconductor Manufacturing International Corp.
- Inventors: JUNZHU CAO; LILY JIANG; CINDY LI; CREEK ZHU
- Web page: https://patentgrep.com/patent/US20130157449A1

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for forming metal gates is provided. In the method, a substrate with a first region and a second region is provided. Dummy gate structures and an ILD layer is formed on the substrate. Dummy gates of the dummy gate structures are removed to form openings respectively within the two regions. Work function layers are respectively formed to overlay the openings. A metal layer is formed on the work function layers and then a CMP process is performed until the ILD layer is exposed, thereby forming the metal gates within the two regions at the same time. Only one CMP process is performed to the metal layer, so that over polishing of the ILD layer may be reduced and thickness of metal gates may be more accurately controlled.

## Claims

### Claim 1

A method for forming metal gates, comprising:
providing a substrate with a first region and a second region;
forming a first dummy gate structure and a second dummy gate structure within the first region and the second region, respectively, wherein the first dummy gate structure includes a first dummy gate and the second dummy gate structure includes a second dummy gate;
forming an interlayer dielectric layer on the substrate exposing the first dummy gate structure and the second dummy gate structure;
removing the first dummy gate of the first dummy gate structure to form a first opening;
forming a first work function layer within the first region over the interlayer dielectric layer and the first opening;
removing the second dummy gate of the second dummy gate structure to form a second opening;
forming a second work function layer within the second region over the interlayer dielectric layer and the first opening;
forming a metal layer on the first work function layer and the second work function layer; and
performing a CMP process to the metal layer, the first work function layer and the second work function layer to form a first metal gate and a second metal gate.

### Claim 2 (depends on 1)

The method according to claim 1, wherein:
a top surface of the interlayer dielectric layer levels with top surfaces of the first dummy gate structure and the second dummy gate structure;
the first work function layer overlays the first opening's sidewalls and bottom surface and the interlayer dielectric layer; and
the second work function layer overlays the second opening's sidewalls and bottom surface and the interlayer dielectric layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein forming a first work function layer within the first region comprises:
forming a first original work function layer overlaying the first opening's sidewalls and bottom surface and the interlayer dielectric layer's top surface;
forming a first sacrificial layer on the first original work function layer; and
removing a portion of the first sacrificial layer and a portion of the first original work function layer within the second region.

### Claim 4 (depends on 1)

The method according to claim 1, wherein forming a second work function layer within the second region comprises:
forming a second original work function layer overlaying the second opening's sidewalls and bottom surface, the exposed interlayer dielectric layer and the remaining first sacrificial layer;
forming a second sacrificial layer on the second original work function layer;
removing a portion of the second sacrificial layer and a portion of the second original work function layer within the first region; and
removing remaining first sacrificial layer and remaining second sacrificial layer.

### Claim 5 (depends on 4)

The method according to claim 4, wherein removing a portion of the second sacrificial layer and a portion of the second original work function layer within the first region comprises: performing a CMP process to the second sacrificial layer and the second original work function layer until the remaining first sacrificial layer is exposed.

### Claim 6 (depends on 4)

The method according to claim 4, wherein the remaining first sacrificial layer and the remaining second sacrificial layer are removed by wet etching or dry etching.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the CMP process is performed by taking the interlayer dielectric layer as a stop layer.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the first work function layer and the second work function layer are different in at least one aspect selected from material, thickness and formation process.

### Claim 9 (depends on 1)

The method according to claim 1, wherein both the first work function layer and the second work function layer include at least one material selected from Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN and TiAlN.

### Claim 10 (depends on 1)

The method according to claim 1, wherein both the first work function layer and the second work function layer are formed by a PVD process or an ALD process.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the first and second sacrificial layers comprise silicon oxide, spin-on glass composition or polymer.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the spin-on glass composition is polysilazane.

### Claim 13 (depends on 6)

The method according to claim 6, wherein the first and second sacrificial layers comprise spin-on glass composition, and the remaining first and second sacrificial layers are removed by a wet etching process by using diluted hydrofluoric acid as an etchant.

### Claim 14 (depends on 1)

The method according to claim 1, wherein the metal layer comprises at least one material selected from Al, Cu, Ti, Ag, Au, Pt and Ni.

### Claim 15 (depends on 1)

The method according to claim 1, wherein the metal layer is formed by sputtering, CVD or electroplating.

### Claim 16 (depends on 3)

The method according to claim 3, further comprising: forming a first diffusion barrier layer overlaying the first opening's sidewalls and bottom surface and the interlayer dielectric layer's top surface before forming the first original work function layer.

### Claim 17 (depends on 4)

The method according to claim 4, further comprising: forming a second diffusion barrier layer overlaying the second opening's sidewalls and bottom surface, the exposed interlayer dielectric layer and the remaining first sacrificial layer before forming the second original work function layer.