# US 2013/0157441 A1 · Method for fabricating semiconductor device

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- Number: US 2013/0157441 A1
- Document ID: US20130157441A1
- Status: Published application
- Kind: A1
- Application number: 13/475,085
- Filed: 2012-05-18
- Published: 2013-06-20
- Earliest claimed: 2011-12-19
- Assignees: Hynix Semiconductor Inc.
- Inventors: Jung-Dae HAN
- Web page: https://patentgrep.com/patent/US20130157441A1

## CPC

- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device fabricating method includes forming an etch target layer and a first hard mask layer over a substrate, forming a second hard mask pattern having lines over the first hard mask layer, forming a third hard mask layer over the second hard mask pattern, forming a sacrificial pattern over the third hard mask layer, forming a cell spacer on sidewalls of the sacrificial pattern, removing the sacrificial pattern, etching the third hard mask layer using the cell spacer as an etch barrier, etching the first hard mask layer using the third hard mask pattern and the second hard mask pattern as etch barriers, forming an elliptical opening having an axis pointing in a second direction by etching the etch target layer, and forming a silicon layer that fills the elliptical opening.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
forming an etch target layer over a substrate;
forming a first hard mask layer over the etch target layer;
forming a second hard mask pattern having lines that extend in a first direction over the first hard mask layer;
forming a third hard mask layer over the second hard mask pattern;
forming a sacrificial pattern having lines that extend in a second direction crossing the first direction in an oblique direction over the third hard mask layer;
forming a cell spacer on sidewalls of the sacrificial pattern;
removing the sacrificial pattern;
etching the third hard mask layer using the cell spacer as an etch barrier to form a third hard mask pattern;
etching the first hard mask layer using the third hard mask pattern and the second hard mask pattern as etch barriers to form a first hard mask pattern;
forming an elliptical opening having an axis extending in the second direction by etching the etch target layer using the first hard mask pattern as an etch barrier; and
forming a silicon layer that fills the elliptical opening.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first hard mask layer includes a nitride layer, and the second hard mask pattern includes a polysilicon layer pattern.

### Claim 3 (depends on 1)

The method of claim 1, wherein the sacrificial pattern includes a carbon layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the sacrificial pattern includes a spin-on-carbon (SOC) layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the cell spacer includes an oxide layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the silicon layer is formed through a selective epitaxial growing (SEG) process.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming of a second hard mask pattern comprises:
forming a second hard mask layer over the etch target layer and the first hard mask layer;
forming a second sacrificial pattern over the second hard mask layer;
forming a spacer on sidewalls of the second sacrificial pattern;
removing the second sacrificial pattern;
etching the second hard mask layer using the spacer as an etch barrier to form the second hard mask pattern; and
removing the spacer.

### Claim 8 (depends on 7)

The method of claim 7, wherein the second sacrificial pattern includes a amorphous carbon or a spin-on-carbon (SOC) layer.

### Claim 9 (depends on 7)

The method of claim 7, wherein the spacer includes an oxide layer.

### Claim 10

A method for fabricating a semiconductor device, comprising:
forming an etch target layer over a substrate having cell regions and peripheral regions;
forming a first hard mask layer over the etch target layer;
forming a second hard mask pattern having lines that extend in a first direction over the first hard mask layer in the cell regions;
forming a third hard mask layer over the second hard mask pattern in the cell regions and over the first hard mask layer in the peripheral regions;
forming a sacrificial pattern having lines that extend in a second direction crossing the first direction in an oblique direction over the third hard mask layer;
forming a cell spacer and a peripheral spacer on sidewalls of the sacrificial pattern;
removing the sacrificial pattern of the cell regions;
etching the third hard mask layer using the cell spacer in the cell regions, and etching the third hard mask using the peripheral spacer and the sacrificial pattern in the peripheral regions as etch barriers to form a third hard mask pattern;
etching the first hard mask layer using the second hard mask pattern of the cell regions and the third hard mask pattern as etch barriers to form a first hard mask pattern;
forming an elliptical cell opening having an axis pointing in the second direction and a peripheral opening having lines that extend in the second direction by etching the etch target layer using the first hard mask pattern as an etch barrier; and
forming a silicon layer filling the elliptical cell opening and the peripheral opening.

### Claim 11 (depends on 10)

The method of claim 10, wherein the peripheral regions have a line width that is the same as the combined line width of the peripheral spacer and the sacrificial pattern in the etching of the third hard mask layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein in the forming of the sacrificial pattern having lines that extend in the second direction crossing the first direction in the oblique direction over the third hard mask layer,
the sacrificial pattern of the peripheral regions is formed through a negative exposure method.

### Claim 13 (depends on 10)

The method of claim 10, wherein the first hard mask layer includes a nitride layer, and the second hard mask pattern includes a polysilicon layer.

### Claim 14 (depends on 10)

The method of claim 10, wherein the sacrificial pattern includes a carbon layer.

### Claim 15 (depends on 10)

The method of claim 10, wherein the cell spacer and the peripheral spacer include an oxide layer.

### Claim 16 (depends on 10)

The method of claim 10, wherein the silicon layer is formed through a selective epitaxial growing (SEG) process.

### Claim 17 (depends on 10)

The method of claim 10, wherein the forming of a second hard mask pattern comprises:
forming a second hard mask layer over the etch target layer and the first hard mask layer;
forming a second sacrificial pattern over the second hard mask layer of the cell regions;
forming a spacer on sidewalls of the second sacrificial pattern of the cell regions;
removing the second sacrificial pattern;
etching the second hard mask layer of the cell region using the spacer as an etch barrier to form the second hard mask pattern; and
removing the spacer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second hard mask layer of the peripheral regions is removed during the etching of the second hard mask layer of the cell region.

### Claim 19 (depends on 17)

The method of claim 17, wherein the second sacrificial pattern includes a amorphous carbon or a spin-on-carbon (SOC) layer.

### Claim 20 (depends on 17)

The method of claim 17, wherein the spacer includes an oxide layer.