# US 2013/0157431 A1 · Structure and method for thermal treatment with epitaxial sicp thermal stability improvement

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- Number: US 2013/0157431 A1
- Document ID: US20130157431A1
- Status: Published application
- Kind: A1
- Application number: 13/332,011
- Filed: 2011-12-20
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chun Hsiung Tsai; Su-Hao Liu; Tsan-Chun Wang
- Web page: https://patentgrep.com/patent/US20130157431A1

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10P 34/422: {using incoherent radiation}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.

## Claims

### Claim 1

A method, comprising:
providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region;
forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack;
replacing the first gate stack with a second gate stack having a high k dielectric material layer; and
thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.

### Claim 2 (depends on 1)

The method of claim 1, wherein the performing a MSA process includes performing a flash-lamp annealing process.

### Claim 3 (depends on 1)

The method of claim 1, wherein each of the first and second wavelets has a peak duration ranging between about 1 millisecond and about 3 milliseconds.

### Claim 4 (depends on 1)

The method of claim 1, wherein the MSA process includes a charging time between the first thermal wavelet and the second thermal wavelet.

### Claim 5 (depends on 1)

The method of claim 1, further includes performing a pre-heating process that is at least partially overlapped with the MSA process.

### Claim 6 (depends on 5)

The method of claim 5, wherein the pre-heating process is extended through a charging time between the first thermal wavelet and the second thermal wavelet.

### Claim 7 (depends on 6)

The method of claim 6, wherein the pre-heating process provides a thermal power tuned according to the charging time such that the substrate temperature is maintained in a temperature range between about 500° C. and about 800° C.

### Claim 8 (depends on 6)

The method of claim 6, wherein the performing a pre-heating process includes implementing a spike rapid thermal annealing (spike RTA) process.

### Claim 9 (depends on 6)

The method of claim 6, wherein each of the first and second thermal wavelets in the MSA process includes a peak temperature ranging between about 1000° C. and about 1250° C.

### Claim 10 (depends on 1)

The method of claim 1, wherein the forming an in-situ phosphorous doped silicon carbide features includes implementing one of a cyclic deposition etch (CDE) process, a selective epitaxial growth (SEG) process and a combined CDE/SEG bi-layer process.

### Claim 11 (depends on 1)

The method of claim 1, wherein the replacing the first gate stack with a second gate stack having a high k dielectric material layer includes
depositing a interlayer dielectric (ILD) layer on the semiconductor substrate;
performing a chemical mechanical polishing (CMP) process to the ILD layer;
etching to remove the first gate stack, resulting a gate trench; and
depositing the high-k dielectric material layer in the gate trench.

### Claim 12 (depends on 1)

The method of claim 1, further comprising implementing a stress memorization technique (SMT) prior to the forming in-situ SiCP features, wherein the SMT includes
performing a pre-amorphized implantation (PAT) process to the semiconductor substrate in the active region;
depositing a dielectric material layer on the semiconductor substrate and the first gate stack; and
performing a thermal annealing process to the semiconductor substrate.

### Claim 13

A method, comprising:
forming a dummy gate stack on a substrate that includes a channel region underlying the dummy gate stack and includes source/drain (S/D) regions interposed by the channel region;
forming source and drain extension (SDE) features in the S/D regions;
performing a first thermal annealing process to the substrate for SDE activation;
etching the substrate in the S/D regions to form recessed regions in the substrate;
forming in-situ doped features on the recessed regions;
removing the dummy gate stack from the channel region;
forming a high k dielectric material layer on the substrate and within the channel region; and
thereafter applying, to the substrate, a millisecond annealing process with a thermal profile having a first thermal wavelet and a second thermal wavelet.

### Claim 14 (depends on 13)

The method of claim 13, further comprising a
performing a pre-amorphized implantation (PAT) process to the substrate in the active region;
depositing a dielectric material layer on the substrate and the first gate stack; and
performing a second thermal annealing process to the substrate for strained effect.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first and second thermal annealing processes each include a spike rapid thermal annealing (spike RTA) process.

### Claim 16 (depends on 13)

The method of claim 13, wherein the forming in-situ doped features on the recessed regions includes forming in-situ phosphorous-doped silicon carbide (SiCP) features.

### Claim 17 (depends on 13)

The method of claim 13, wherein
the millisecond annealing process includes a flash lamp annealing (FLA) process; and
the first and second thermal wavelets are separated by a charging time greater than about 10 seconds.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first and second thermal wavelets each includes a peak temperature ranging between about 1000° C. and about 1250° C. and a time duration less than about 10 milliseconds.

### Claim 19 (depends on 17)

The method of claim 17, wherein the thermal profile of the millisecond annealing process further includes a third thermal wavelet after the second thermal wavelet separated from the second thermal wavelet by another changing time.

### Claim 20

A method of making a semiconductor structure, comprising:
forming a dummy gate stack on a semiconductor substrate that includes a channel region and source/drain (S/D) regions interposed by the channel region;
etching the substrate in the S/D regions to form recessed regions in the semiconductor substrate;
forming in-situ phosphorous doped silicon carbide features on the recessed regions;
forming an interlayer dielectric (ILD) layer on the semiconductor substrate and the dummy gate stack;
removing the dummy gate stack, resulting in a gate trench in the ILD layer;
forming a high k dielectric material layer in the gate trench; and
performing a millisecond annealing (MSA) process to the high k dielectric material, wherein the MSA process includes a thermal profile having a first thermal wavelet and a second thermal wavelet separated from the first thermal wavelet by a charging time.