# US 2013/0157428 A1 · Methods of Manufacturing Semiconductor Devices Including Transistors

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- Number: US 2013/0157428 A1
- Document ID: US20130157428A1
- Status: Published application
- Kind: A1
- Application number: 13/613,868
- Filed: 2012-09-13
- Published: 2013-06-20
- Earliest claimed: 2011-12-14
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Sung-kweon Baek; Jin-soak Kim; Gab-jin Nam; Ji-young Min; Eun-ae Chang
- Web page: https://patentgrep.com/patent/US20130157428A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10P 32/20: Diffusion for doping of insulating layers
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device includes forming a gate insulation layer pattern on a substrate, forming a sacrificial layer including impurities on the gate insulation layer pattern, annealing the sacrificial layer so that the impurities in the sacrificial layer diffuse into the gate insulation layer pattern, removing the sacrificial layer, and forming a gate electrode on the gate insulation layer pattern.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a gate insulation layer on a substrate;
forming a sacrificial layer containing impurities on the gate insulation layer;
annealing the sacrificial layer to cause the impurities in the sacrificial layer to diffuse into the gate insulation layer;
removing the sacrificial layer; and
forming a gate electrode on the gate insulation layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the impurities comprise boron or phosphorus.

### Claim 3 (depends on 1)

The method of claim 1, wherein the annealing process is performed at a temperature of about 900° C. to about 1100° C.

### Claim 4 (depends on 1)

The method of claim 1, wherein the sacrificial layer comprises a polysilicon layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the sacrificial layer doped with impurities comprises providing the impurities in-situ while forming the sacrificial layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the sacrificial layer is formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the sacrificial layer comprises:
forming a polysilicon layer on the gate insulation layer; and
implanting impurities into the polysilicon layer using an ion implantation process.

### Claim 8 (depends on 7)

The method of claim 7, wherein the ion implantation process is performed using an impurity dose range between 1014 and 1017 atoms/cm2.

### Claim 9 (depends on 1)

The method of claim 1, wherein forming the sacrificial layer comprises:
forming a buffer layer pattern on the gate insulation layer; and
forming the sacrificial layer on the buffer layer pattern.

### Claim 10 (depends on 9)

The method of claim 9, wherein the buffer layer pattern comprises titanium, titanium nitride, tantalum, tantalum nitride, and/or ruthenium.

### Claim 11

A method of manufacturing a semiconductor device, comprising:
forming a trench on a substrate;
forming a gate insulation layer on an inner wall of the trench;
forming a sacrificial layer including impurities on the gate insulation layer;
annealing the sacrificial layer to cause the impurities in the sacrificial layer diffuse into the gate insulation layer;
removing the sacrificial layer; and
forming a gate electrode on the gate insulation layer.

### Claim 12 (depends on 11)

The method of claim 11, further comprising forming a buffer layer on the gate insulation layer, wherein the sacrificial layer is formed on the buffer layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the gate electrode comprises:
forming a gate electrode layer to at least partially fill the trench on the buffer layer; and
performing an etch-back process on the gate electrode layer until a top surface of the gate electrode layer is lower than a top surface of the substrate.

### Claim 14 (depends on 11)

The method of claim 11, further comprising forming an impurity region on the substrate adjacent to the trench by performing an ion implantation process on the substrate.

### Claim 15 (depends on 11)

The method of claim 11, wherein the sacrificial layer comprises a polysilicon layer.

### Claim 16

A method of manufacturing a semiconductor device including a high-k gate insulation layer, comprising:
forming a buffer layer on the high-k gate insulation layer;
forming a sacrificial layer containing impurities on the buffer layer;
diffusing impurities from the sacrificial layer through the buffer layer and into the high-k gate insulation layer;
removing the sacrificial layer; and
forming a gate electrode on the buffer layer.