# US 2013/0157425 A1 · Semiconductor device and manufacturing method thereof

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- Number: US 2013/0157425 A1
- Document ID: US20130157425A1
- Status: Published application
- Kind: A1
- Application number: 13/760,397
- Filed: 2013-02-06
- Published: 2013-06-20
- Earliest claimed: 2010-01-13
- Assignees: Sony Corporation
- Inventors: Rui MORIMOTO
- Web page: https://patentgrep.com/patent/US20130157425A1

## CPC

- H10W 40/037: {Assembling together parts thereof}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 89/10: Integrated device layouts
- H10W 40/28: comprising Peltier coolers
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes: a cooling function component including an active region made of an impurity region and formed on a surface of a semiconductor layer, an N-type gate made of a semiconductor including an N-type impurity, a P-type gate made of a semiconductor including a P-type impurity, a first metal wiring connected to the N-type gate, the P-type gate and the active region, a second metal wiring connected to the P-type gate and the N-type gate, and a heat releasing portion connected to the second metal wiring for releasing heat to the outside.

## Claims

### Claim 1

A manufacturing method of a semiconductor device, comprising the steps of:
forming a semiconductor film to be a gate on a semiconductor layer;
implanting an N-type impurity into one part of the semiconductor film and implanting a P-type impurity into the other part of the semiconductor film;
forming an N-type gate and a P-type gate respectively by patterning the semiconductor film;
forming an active region made of an impurity region on the surface of the semiconductor layer;
forming a first metal wiring connected to the N-type gate, the P-type gate and the active region and forming a second metal wiring connected to the P-type gate and the N-type gate; and
forming a heat releasing portion connected to the second metal wiring for releasing heat to the outside.

### Claim 2 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1,
wherein the step of forming the N-type gate and the P-type gate respectively by patterning the semiconductor film is performed at the same time as the step of forming the gate of a transistor on the semiconductor layer.

### Claim 3 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1,
wherein a step of forming a contact layer electrically connected to the second impurity region as well as forming a metal layer which is the same layer as the contact layer forming the first metal wiring and the second metal wiring after performing the step of forming the active region and the step of forming the second impurity region forming the active component on the semiconductor layer.

### Claim 4 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1,
wherein the semiconductor layer, the N-type gate and the P-type gate are made of silicon, further comprising the steps of:
forming a silicide block made of an insulator at part of surfaces of the N-type gate and the P-type gate and forming a silicide made of a metal element and silicon on two portions on surfaces of the N-type gate and the P-type gate separated by the silicide block as well as the surface of the active region after the step of forming the active region,
forming the first metal wiring connected to the silicide at one of the two portions as well as at the surface of the active region; and
forming the second metal wiring connected to the silicide at the other of the two portions.

### Claim 5 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1,
wherein the N-type gate and the P-type gate are respectively formed on an component isolation layer formed in the semiconductor layer.