# US 2013/0157424 A1 · Method for improved mobility using hybrid orientaion technology (HOT) in conjunction with

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- Number: US 2013/0157424 A1
- Document ID: US20130157424A1
- Status: Published application
- Kind: A1
- Application number: 13/762,656
- Filed: 2013-02-08
- Published: 2013-06-20
- Earliest claimed: 2009-10-16
- Assignees: Texas Instruments Incorporated
- Inventors: Alexander H. Owens
- Web page: https://patentgrep.com/patent/US20130157424A1

## CPC

- H10D 86/01: Manufacture or treatment
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation.

## Claims

### Claim 1

A method comprising:
obtaining a substrate structure comprising:
a first substrate;
a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer; and
an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate, wherein the second substrate has a higher hole mobility than the epitaxial layer, wherein the epitaxial layer has a higher electron mobility than the second substrate, and wherein the hole and electron mobilities are bulk properties; and
forming first and second transistors, the first transistor formed at least partially in the second substrate, the second transistor formed at least partially in or over the epitaxial layer, at least one of the transistors configured to receive one or more signals of at least about 5V.

### Claim 2 (depends on 1)

The method of claim 1, wherein obtaining the substrate structure comprises:
removing a portion of second substrate material;
forming a spacer on a side of the second substrate; and
forming the epitaxial layer in an area where the second substrate material was removed.

### Claim 3 (depends on 2)

The method of claim 2, wherein obtaining the substrate structure further comprises:
forming trenches to isolate the second substrate and the epitaxial layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein:
the first substrate has a first crystalline orientation; and
the second substrate has a second crystalline orientation.

### Claim 5 (depends on 4)

The method of claim 4, wherein the epitaxial layer has the first crystalline orientation.

### Claim 6 (depends on 4)

The method of claim 4, wherein:
the first substrate comprises p-type silicon having a (100) crystalline orientation;
the second substrate comprises n-type silicon having a (110) crystalline orientation;
the epitaxial layer comprises silicon germanium; and
a cap located over the epitaxial layer comprises p-type silicon, the second transistor formed at least partially in the cap.