# US 2013/0156146 A1 · Trigger Circuits and Event Counters for an IC

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- Number: US 2013/0156146 A1
- Document ID: US20130156146A1
- Status: Published application
- Kind: A1
- Application number: 13/645,314
- Filed: 2012-10-04
- Published: 2013-06-20
- Earliest claimed: 2008-08-04
- Assignees: Tabula, Inc.
- Inventors: Brad Hutchings; Jason Redgrave; Dai Huang; Steven Teig
- Web page: https://patentgrep.com/patent/US20130156146A1

## CPC

- G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom
- G06M 3/00: Counters with additional facilities
- H03K 19/17736: Structural details of routing resources
- H03K 19/017581: {programmable}
- H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables
- H03K 19/17748: Structural details of configuration resources
- H03K 19/1776: for memories
- H03K 19/17764: for reliability
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06M: COUNTING MECHANISMS; COUNTING OF OBJECTS NOT OTHERWISE PROVIDED FOR
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.

## Claims

### Claim at position 1

1-15. (canceled)

### Claim 16

An integrated circuit (“IC”) comprising:
a) a plurality of groups configurable circuits for configurably performing operations based on configuration data; and
b) at least one event counter circuit for receiving an event signal that indicates that an operational event has occurred in the IC and adjusting a count value stored by said event counter circuit upon receiving said event signal.

### Claim 17 (depends on 16)

The IC of claim 16 further comprising a plurality of event counters.

### Claim 18 (depends on 16)

The IC of claim 16, wherein said event count value of said event counter is for being read while a particular group of configurable circuits operates.

### Claim 19 (depends on 16)

The IC of claim 16, wherein said adjusting comprises one of an increment and a decrement operation.

### Claim 20 (depends on 16)

The IC of claim 16, wherein said event counter circuit is associated with an initial count value that is reset upon the event counter circuit receiving a signal indicating that the operational event has not occurred.

### Claim at position 7

21-23. (canceled)

### Claim 24

An integrated circuit (“IC”) comprising:
a) an event counter circuit for counting a number of occurrences of an operational event in the IC;
b) a trigger circuit for receiving a signal from the event counter circuit that indicates that the operational event has occurred a predetermined number of times; and
c) a trace buffer for storing a set of data upon said trigger circuit receiving said signal indicating that said operational event has occurred the predetermined number of times.

### Claim 25 (depends on 24)

The IC of claim 24, wherein the trace buffer has a pre-trigger mode, wherein the trace buffer does not overwrite any data stored by the trace buffer upon receiving said signal.

### Claim 26 (depends on 24)

The IC of claim 24, wherein the trace buffer has a post-trigger mode, wherein the trace buffer begins storing data upon receiving said signal.

### Claim 27 (depends on 24)

The IC of claim 24, wherein said data stored by the trace buffer is user design data of a user design implemented by the IC.

### Claim at position 12

28-50. (canceled)