# US 2013/0156124 A1 · System and method for frequency diversity > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0156124 A1 - Document ID: US20130156124A1 - Status: Published application - Kind: A1 - Application number: 13/767,834 - Filed: 2013-02-14 - Published: 2013-06-20 - Earliest claimed: 2005-07-29 - Assignees: QUALCOMM Incorporated - Inventors: Michael Mao Wang; Murali Ramaswamy Chari; Ashok Mantravadi; Fuyun Ling; Rajiv Vijayan; Raghuraman Krishnamoorthi - Web page: https://patentgrep.com/patent/US20130156124A1 ## CPC - H04L 27/2626: {Arrangements specific to the transmitter only} - H03M 13/258: {with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]} - H03M 13/271: {Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations} - H03M 13/31: combining coding for error detection or correction and efficient use of the spectrum (without error detection or correction H03M5/14 {, H03M5/145}) - H04L 1/0071: {Use of interleaving (interleaving per se H03M13/27)} - H04L 5/0044: {Allocation of payload; Allocation of data channels, e.g. PDSCH or PUSCH} - H04L 5/0064: {Rate requirement of the data, e.g. scalable bandwidth, data priority} - H04L 5/0083: {symbol-by-symbol} - H04L 27/2601: {Multicarrier modulation systems} - H04L 27/2634: {Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation} - H03M 13/2957: {Turbo codes and decoding} - H04L 1/04: using frequency diversity - H04L 5/0007: {the frequencies being orthogonal, e.g. OFDM(A) or DMT} - H04L 5/0042: {Intra-user or intra-terminal allocation} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A system and method for frequency diversity uses interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes. Subcarriers of one or more interlaces are interleaved in a bit reversal fashion and the one or more interlaces are interleaved in the bit reversal fashion. ## Claims ### Claim 1 A method for interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, comprising: interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; and interleaving the one or more interlaces such that the mapped symbols are interleaved into a second order. ### Claim 2 (depends on 1) The method of claim 1, wherein the bit reversal fashion is a reduce-set bit reversal operation if the number of subcarriers is not a power of two. ### Claim 3 (depends on 2) The method of claim 2, wherein said interleaving subcarriers comprises: creating an empty subcarrier index vector (SCIV); initializing an index variable (i) to zero; converting i to its bit reversed nine-bit value (ibr); appending ibr into the SCIV, if ibr is less than 511; and incrementing i by one and repeat the converting, appending and incrementing, if is less than 511. ### Claim 4 (depends on 1) The method of claim 1, wherein the interleaving subcarriers of one or more interlaces in a bit reversal fashion involves mapping symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table. ### Claim 5 (depends on 1) The method of claim 1, wherein the interleaving the one or more interlaces occurs every OFDM symbol. ### Claim 6 An apparatus for interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, comprising: a processor configured to interleave subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; and a processor configured to interleave the one or more interlaces in the bit reversal fashion such that the mapped symbols are interleaved into a second order;. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the bit reversal fashion is a reduce-set bit reversal operation if the number of subcarriers is not a power of two. ### Claim 8 (depends on 6) The apparatus of claim 6, wherein the number of interlaces is eight. ### Claim 9 (depends on 6) The apparatus of claim 6, wherein the processor configured to interleave subcarriers of one or more interlaces in a bit reversal fashion is further configured to map symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table. ### Claim 10 (depends on 6) The apparatus of claim 6, wherein the interleaving the one or more interlaces occurs every OFDM symbol. ### Claim 11 A processor executing instructions in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, the instructions comprising: interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; and interleaving the one or more interlaces in the bit reversal fashion such that the mapped symbols are interleaved into a second order. ### Claim 12 (depends on 11) The processor of claim 11, wherein the bit reversal fashion is a reduce-set bit reversal operation if the number of subcarriers is not a power of two. ### Claim 13 (depends on 11) The processor of claim 11, wherein the number of interlaces is eight. ### Claim 14 (depends on 11) The processor of claim 11, wherein the interleaving subcarriers of one or more interlaces in a bit reversal fashion involves mapping symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table. ### Claim 15 (depends on 11) The processor of claim 11, wherein the interleaving the one or more interlaces occurs every OFDM symbol. ### Claim 16 An apparatus for interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, comprising: means for interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; and means for interleaving the one or more interlaces in the bit reversal fashion such that the mapped symbols are interleaved into a second order. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the bit reversal fashion is a reduce-set bit reversal operation if the number of subcarriers is not a power of two. ### Claim 18 (depends on 16) The apparatus of claim 16, wherein the number of interlaces is eight. ### Claim 19 (depends on 16) The apparatus of claim 16, wherein the means for interleaving subcarriers of one or more interlaces in a bit reversal fashion comprises means for mapping symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table. ### Claim 20 (depends on 16) The apparatus of claim 16, wherein the means for interleaving the one or more interlaces occurs every OFDM symbol. ### Claim 21 A system for interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, comprising: a processor configured to interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; and a processor configured to interleave the one or more interlaces in the bit reversal fashion such that the mapped symbols are interleaved into a second order. ### Claim 22 (depends on 21) The system of claim 21, wherein the bit reversal fashion is a reduce-set bit reversal operation if the number of subcarriers is not a power of two. ### Claim 23 (depends on 22) The system of claim 22, wherein said processor configured to interleave subcarriers is further configured to: create an empty subcarrier index vector (SCIV); initialize an index variable (i) to zero; convert i to its bit reversed nine-bit value (ibr);append ibr into the SCIV, if ibr is less than 511; and increment i by one and repeat the converting, appending and incrementing, if i is less than 511. ### Claim 24 (depends on 21) The system of claim 21, wherein the processor configured to interleave the one or more interlaces is further configured to: for a 1K FFT size, map interlaces in four consecutive OFDM symbols to slot s by mapping an ith modulation symbol, where i {0, 1, . . . 499}, to a jth subcarrier of interlace Ik(s), wherein k=BR2(SCIV[i]mod 4), j=floor(SCIV[i]/4), and BR2(*) is a bit reversal operation for two bits. ### Claim 25 (depends on 21) The system of claim 21, wherein the processor configured to interleave the one or more interlaces is further configured to: for a 2K FFT size, map interlaces in 2 consecutive OFDM symbols to slot s by mapping an ith modulation symbol, where i {0, 1, . . . 499}, to a jth subcarrier of interlace Ik(s), wherein k=(SCIV[i]mod 2), and j=floor(SCIV[i]/2).