# US 2013/0156087 A1 · A decision feedback equalization scheme with minimum correction delay > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0156087 A1 - Document ID: US20130156087A1 - Status: Published application - Kind: A1 - Application number: 13/772,872 - Filed: 2013-02-21 - Published: 2013-06-20 - Earliest claimed: 2008-10-24 - Assignees: STMicroelectronics S.r.l. - Inventors: SIMONE ERBA; MASSIMO POZZONI - Web page: https://patentgrep.com/patent/US20130156087A1 ## CPC - H04L 25/03885: {adaptive} - H04L 25/0307: {using blind adaptation} - H04L 25/03063: {using fractionally spaced delay lines or combinations of fractionally and integrally spaced taps} - H04L 2025/03356: {Baseband transmission} - H04L 2025/03579: {Modifying the tap spacing} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer. ## Claims ### Claim at position 1 1-5. (canceled) ### Claim 6 A decision feedback equalizer comprising: a correction circuit configured to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit, said correction circuit comprising a first multiplexer configured to be controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for reducing the intersymbol interference, and a first pair of latches configured to receive as input the received bit and being clocked in phase opposition by the clock signal to be transparent to generate respective latched replicas of the received bit during respective active phases of the clock signal, with the respective latched replicas being input to said first multiplexer. ### Claim 7 (depends on 6) The decision feedback equalizer of claim 6, wherein the sampled value of the incoming bit being corrected by said correction circuit is based on two preceding bits; and wherein said correction circuit further comprises: a second multiplexer configured to be controlled by the clock signal to generate a digital level representative of a sign of a second correction coefficient to be subtracted from the sampled value of the incoming bit for reducing the intersymbol interference therein; and a second pair of latches coupled in cascade with said first pair of latches to receive as input the latched replicas generated by said first pair of latches, said second pair of latches being clocked in phase opposition by the clock signal to generate latched replicas with respect to said first pair of latches, the latched replicas of said second pair of latches being input to said second multiplexer. ### Claim 8 (depends on 6) The decision feedback equalizer of claim 6, further comprising a first pair of amplifiers coupled between said first pair of latches and said first multiplexer, said first pair of amplifiers configured to amplify and saturate the latched replicas to be input to said first multiplexer. ### Claim 9 (depends on 6) The decision feedback equalizer of claim 6, wherein said correction circuit further comprises a logic comparator configured to receive a sampled level corrected from the intersymbol interference, and to generate the received bit responsive thereto. ### Claim 10 (depends on 6) The decision feedback equalizer of claim 6, further comprising a pair of flip-flops with a programmable threshold set to opposite logic levels and clocked in phase opposition with the clock signal, said pair of flip-flops configured to generate respective error signals as a difference between the sampled value corrected from the intersymbol interference and the respective threshold. ### Claim 11 A decision feedback equalizer comprising: a correction circuit configured to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit, said correction circuit comprising a first multiplexer configured to be controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for reducing the intersymbol interference, a first pair of latches configured to receive as input the received bit and being clocked in phase opposition by the clock signal to be transparent to generate respective latched replicas of the received bit during respective active phases of the clock signal, with the respective latched replicas being input to said first multiplexer, and a first pair of amplifiers coupled between said first pair of latches and said first multiplexer. ### Claim 12 (depends on 11) The decision feedback equalizer of claim 11, wherein the sampled value of the incoming bit being corrected by said correction circuit is based on two preceding bits; and wherein said correction circuit further comprises: a second multiplexer configured to be controlled by the clock signal to generate a digital level representative of a sign of a second correction coefficient to be subtracted from the sampled value of the incoming bit for reducing the intersymbol interference therein; and a second pair of latches coupled in cascade with said first pair of latches to receive as input the latched replicas generated by said first pair of latches, said second pair of latches being clocked in phase opposition by the clock signal to generate latched replicas with respect to said first pair of latches, the latched replicas of said second pair of latches being input to said second multiplexer. ### Claim 13 (depends on 11) The decision feedback equalizer of claim 11, wherein said correction circuit further comprises a logic comparator configured to receive a sampled level corrected from the intersymbol interference, and to generate the received bit responsive thereto. ### Claim 14 (depends on 11) The decision feedback equalizer of claim 11, further comprising a pair of flip-flops with a programmable threshold set to opposite logic levels and clocked in phase opposition with the clock signal, said pair of flip-flops configured to generate respective error signals as a difference between the sampled value corrected from the intersymbol interference and the respective threshold. ### Claim 15 A receiver comprising: a decision feedback equalizer configured to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit, said decision feedback equalizer comprising a first multiplexer configured to be controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for reducing the intersymbol interference, and a first pair of latches configured to receive as input the received bit and being clocked in phase opposition by the clock signal to be transparent to generate respective latched replicas of the received bit during respective active phases of the clock signal, with the respective latched replicas being input to said first multiplexer. ### Claim 16 (depends on 15) The receiver of claim 15, wherein the sampled value of the incoming bit being corrected by said decision feedback equalizer is based on two preceding bits; and wherein said decision feedback equalizer further comprises: a second multiplexer configured to be controlled by the clock signal to generate a digital level representative of a sign of a second correction coefficient to be subtracted from the sampled value of the incoming bit for reducing the intersymbol interference therein; and a second pair of latches coupled in cascade with said first pair of latches to receive as input the latched replicas generated by said first pair of latches, said second pair of latches being clocked in phase opposition by the clock signal to generate latched replicas with respect to said first pair of latches, the latched replicas of said second pair of latches being input to said second multiplexer. ### Claim 17 (depends on 15) The receiver of claim 15, further comprising a first pair of amplifiers coupled between said first pair of latches and said first multiplexer, said first pair of amplifiers to amplify and saturate the latched replicas to be input to said first multiplexer. ### Claim 18 (depends on 15) The receiver of claim 15, wherein said decision feedback equalizer further comprises a logic comparator configured to receive a sampled level corrected from the intersymbol interference, and to generate the received bit responsive thereto. ### Claim 19 (depends on 15) The receiver of claim 15, wherein said decision feedback equalizer further comprises a pair of flip-flops with a programmable threshold set to opposite logic levels and clocked in phase opposition with the clock signal, said pair of flip-flops configured to generate respective error signals as a difference between the sampled value corrected from the intersymbol interference and the respective threshold. ### Claim 20 A method for operating a decision feedback equalizer comprising a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit, the correction circuit comprising a first multiplexer and a first pair of latches coupled thereto, the method comprising: controlling the first multiplexer with the clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for reducing the intersymbol interference; and controlling the first pair of latches to receive as input the received bit and clocking the first pair of latches ed in phase opposition by the clock signal to be transparent to generate respective latched replicas of the received bit during respective active phases of the clock signal, with the respective latched replicas being input to the first multiplexer. ### Claim 21 (depends on 20) The method of claim 20, wherein the sampled value of the incoming bit being corrected by the correction circuit is based on two preceding bits; and wherein the correction circuit further comprises a second multiplexer and a second pair of latches coupled in cascade with the first pair of latches, and further comprising: controlling the second multiplexer with the clock signal to generate a digital level representative of a sign of a second correction coefficient to be subtracted from the sampled value of the incoming bit for reducing the intersymbol interference therein; and controlling the second pair of latches to receive as input the latched replicas generated by the first pair of latches, the second pair of latches being clocked in phase opposition by the clock signal to generate latched replicas with respect to the first pair of latches, the latched replicas of the second pair of latches being input to the second multiplexer. ### Claim 22 (depends on 20) The method of claim 20, wherein the correction circuit further comprises a first pair of amplifiers coupled between the first pair of latches and the first multiplexer, the first pair of amplifiers to amplify and saturate the latched replicas to be input to the first multiplexer. ### Claim 23 (depends on 20) The method of claim 20, wherein the correction circuit further comprises a logic comparator to receive a sampled level corrected from the intersymbol interference, and to generate the received bit responsive thereto. ### Claim 24 (depends on 20) The method of claim 20, wherein the correction circuit further comprises a pair of flip-flops with a programmable threshold set to opposite logic levels and clocked in phase opposition with the clock signal, the pair of flip-flops to generate respective error signals as a difference between the sampled value corrected from the intersymbol interference and the respective threshold.