# US 2013/0156084 A1 · Rectifier, received signal strength indicator, and receiver

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- Number: US 2013/0156084 A1
- Document ID: US20130156084A1
- Status: Published application
- Kind: A1
- Application number: 13/716,443
- Filed: 2012-12-17
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Electronics and Telecommunications Research Institute
- Inventors: Hoyong KANG; Nguyen Trung KEIN; Se Han KIM; Tae Joon PARK; Wun-Cheol JEONG; Chang Sub SHIN; In Hwan LEE; Cheol Sig PYO
- Web page: https://patentgrep.com/patent/US20130156084A1

## CPC

- H03F 3/45071: {with semiconductor devices only}
- H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)}
- H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03F 3/45659: {Controlling the loading circuit of the differential amplifier}
- H03F 3/45973: {by using a feedback circuit}
- H04B 17/318: Received signal strength
- H02M 7/23: arranged for operation in parallel {(H02M7/2176 takes precedence)}
- H03F 2203/45008: the addition of two signals being made by a resistor addition circuit for producing the common mode signal
- H03F 2203/45082: the common mode signal being taken or deducted from the one or more outputs of the differential amplifier
- H03F 2203/45138: Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
- H03F: AMPLIFIERS
- H04B: TRANSMISSION
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A received signal strength indicator is provided. The received signal strength indicator includes a plurality of differential amplifiers forming an amplifier chain for amplifying differential signals and a plurality of rectifiers for rectifying signals output from the plurality of differential amplifiers and the differential signals, and a low pass filter for combining the signals rectified by the plurality of rectifiers to output received signal strength. Each rectifier includes a class AB voltage-current converter for converting a differential voltage into a current, and two triode transistors.

## Claims

### Claim 1

A rectifier comprising:
a first transistor including a gate electrode connected to an input voltage;
a second transistor including a gate electrode connected to a second input voltage;
a third transistor including a source electrode connected to a source electrode of the first transistor, a drain electrode connected to a source electrode of the second transistor, and a gate electrode connected to the first input voltage; and
a fourth transistor including a source electrode connected to the source electrode of the first transistor, a drain electrode connected to the source electrode of the second transistor, and a gate electrode connected to the second input voltage.

### Claim 2 (depends on 1)

The rectifier of claim 1, further comprising:
a fifth transistor including a gate electrode connected to a drain electrode of the first transistor; and
a sixth transistor including a gate electrode connected to a source electrode of the fifth transistor.

### Claim 3 (depends on 2)

The rectifier of claim 2, further comprising:
a seventh transistor including a gate electrode connected to a drain electrode of the second transistor;
an eighth transistor including a gate electrode connected to a source electrode of the seventh transistor; and
a ninth transistor including a gate electrode connected to a drain electrode of the eighth transistor and a drain electrode connected to a drain electrode of the sixth transistor.

### Claim 4 (depends on 3)

The rectifier of claim 3, further comprising:
a tenth transistor including a gate electrode connected to a bias voltage and a drain electrode connected to the drain electrode of the firth transistor; and
an eleventh transistor including a gate electrode connected to a bias voltage and a drain electrode connected to the drain electrode of the second transistor.

### Claim 5 (depends on 4)

The rectifier of claim 4, further comprising:
a twelfth transistor including a drain electrode connected to the source electrode of the first transistor and a gate electrode connected to the source electrode of the fifth transistor; and
a thirteenth transistor including a drain electrode connected to the source electrode of the second transistor and a gate electrode connected to the source electrode of the seventh transistor.

### Claim 6 (depends on 5)

The rectifier of claim 5, further comprising:
a fourteenth transistor including a drain electrode connected to the source electrode of the seventh transistor and a gate electrode connected to the source electrode of the seventh transistor; and
a fifteenth transistor including a drain electrode connected to the source electrode of the fifth transistor and a gate electrode connected to the source electrode of the fifth transistor.

### Claim 7 (depends on 6)

The rectifier of claim 6, further comprising
a sixteenth transistor including a drain electrode connected to the drain electrode of the eighth transistor and a gate electrode connected to the drain electrode of the eighth transistor.

### Claim 8

A rectifier comprising:
a class AB voltage-current converter including a first transistor of which a gate electrode is connected to a first input voltage and a second transistor of which a gate electrode is connected to a second input voltage;
a third transistor including a source electrode connected to a source electrode of the first transistor, a drain electrode connected to a source electrode of the second transistor, and a gate electrode connected to the first input voltage; and
a fourth transistor including a source electrode connected to the source electrode of the first transistor, a drain electrode connected to the source electrode of the second transistor, and a gate electrode connected to the second input voltage.

### Claim 9 (depends on 8)

The rectifier of claim 8, further comprising:
a fifth transistor including a gate electrode connected to a drain electrode of the first transistor; and
a sixth transistor including a gate electrode connected to a source electrode of the fifth transistor.

### Claim 10 (depends on 9)

The rectifier of claim 9, further comprising:
a seventh transistor including a gate electrode connected to the source electrode of the second transistor;
an eighth transistor including a gate electrode connected to a source electrode of the seventh transistor; and
a ninth transistor including a gate electrode connected to a drain electrode of the eighth transistor and a drain electrode connected to the drain electrode of the fourth transistor.

### Claim 11

A received signal strength indicator, comprising:
a plurality of differential amplifiers for forming an amplifier chain that amplifies differential signals;
a plurality of rectifiers for rectifying output signals from the plurality of differential amplifiers and the differential signals, respectively; and
a first low pass filter for combining output signals from the plurality of rectifiers and outputting received signal strength,
wherein at least one input among inputs for the plurality of rectifiers includes a first input voltage and a second input voltage, and
at least one among the plurality of rectifiers includes:
a first transistor including a gate electrode connected to the first input voltage; and
a second transistor including a source electrode connected to a source electrode of the first transistor, a drain electrode connected to a drain electrode of the first transistor, and a gate electrode connected to the second input voltage.

### Claim 12 (depends on 11)

The received signal strength indicator of claim 11, wherein the at least one among the plurality of rectifiers further includes:
a third transistor including a gate electrode connected to the first input voltage and a source electrode connected to the source electrode of the first transistor; and
a fourth transistor including a gate electrode connected to the second input voltage and a source electrode connected to the drain electrode of the first transistor.

### Claim 13 (depends on 12)

The received signal strength indicator of claim 12, further comprising:
a fifth transistor including a gate electrode connected to a drain electrode of the third transistor; and
a sixth transistor including a gate electrode connected to a source electrode of the fifth transistor.

### Claim 14 (depends on 13)

The received signal strength indicator of claim 13, further comprising:
a seventh transistor including a gate electrode connected to a drain electrode of the fourth transistor;
an eighth transistor including a gate electrode connected to a source electrode of the seventh transistor; and
a ninth transistor including a gate electrode connected to a drain electrode of the eighth transistor and a drain electrode connected to a drain electrode of the sixth transistor.

### Claim 15 (depends on 12)

The received signal strength indicator of claim 12, wherein
at least one among the plurality of differential amplifiers is provided with a third input voltage and outputs a first output voltage, and
at least one among the plurality of differential amplifiers includes:
a fifth transistor including a gate electrode connected to the third input voltage and a drain electrode connected to the first output voltage; and
a sixth transistor including a drain electrode connected to the drain electrode of the sixth transistor.

### Claim 16 (depends on 15)

The received signal strength indicator of claim 15, wherein
at least one among the plurality of differential amplifiers is further provided with a fourth input voltage and further outputs a second output voltage, and
at least one among the plurality of differential amplifiers includes:
a seventh transistor including a gate electrode connected to the fourth input voltage and a drain electrode connected to the second output voltage;
an eighth transistor including a drain electrode connected to the drain electrode of the seventh transistor; and
a ninth transistor including a gate electrode connected to a bias voltage.

### Claim 17 (depends on 16)

The received signal strength indicator of claim 16, wherein
the at least one among the plurality of differential amplifiers further includes:
a first resistor including a terminal connected to the drain electrode of the sixth transistor;
a second resistor including a terminal connected to the drain electrode of the eighth transistor and the other terminal connected to the other terminal of the first resistor;
a tenth transistor including a gate electrode connected to a gate electrode of the sixth transistor and a drain electrode connected to the gate electrode of the sixth transistor;
an eleventh transistor including a drain electrode connected to the drain electrode of the tenth transistor and a gate electrode connected to the other terminal of the first resistor;
a twelfth transistor including a source electrode connected to a source electrode of the eleventh transistor and a gate electrode connected to a reference voltage; and
a thirteenth transistor including a drain electrode connected to the source electrode and a gate electrode connected to the bias voltage.

### Claim 18 (depends on 12)

The received signal strength indicator of claim 12, further comprising:
a second low pass filter; and
a fifth transistor.

### Claim 19

A receiver, comprising:
a first low pass filter for filtering an in-phase signal;
a second low pass filter for filtering a quadrature phase signal; and
a received signal strength indicator,
wherein the received signal strength indicator includes:
a plurality of differential amplifiers forming an amplifier chain that uses the filtered in-phase signal and the filtered quadrature phase signal as differential signals and amplifies the differential signals; and
a plurality of rectifiers for rectifying output signals from the plurality of differential amplifiers and the differential signals, respectively,
wherein at least one among the plurality of rectifiers includes:
a first transistor including a gate electrode connected to the first input voltage; and
a second transistor including a source electrode connected to a source electrode of the first transistor, a drain electrode connected to a drain electrode of the first transistor, and a gate electrode connected to the second input voltage.

### Claim 20 (depends on 19)

The receiver of claim 19, wherein
the at least one among the plurality of rectifiers further includes:
a third transistor including a gate electrode connected to the first input voltage and a source electrode connected to the source electrode of the first transistor; and
a second transistor including a gate electrode connected to the second input voltage and a source electrode connected to the drain electrode of the first transistor.