# US 2013/0156076 A1 · Circuits and Methods for a Combined Phase Detector

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- Number: US 2013/0156076 A1
- Document ID: US20130156076A1
- Status: Published application
- Kind: A1
- Application number: 13/549,262
- Filed: 2012-07-13
- Published: 2013-06-20
- Earliest claimed: 2011-07-13
- Assignees: The Trustees of Columbia University in the City of New York
- Inventors: Peter R. Kinget; Chunwei Hsu; Shih-An Yu; Karthik Tripurari
- Web page: https://patentgrep.com/patent/US20130156076A1

## CPC

- H04L 27/18: Phase-modulated carrier systems, i.e. using phase-shift keying (H04L27/32 takes precedence)
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump}
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03L 7/235: {Nested phase locked loops}
- H03L 7/0893: {the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

Circuits and methods for a combined phase detector are provided. In some embodiments, circuits for a combined phase detector are provided, the circuits comprising: a tri-state phase frequency detector and charge pump that receives a reference signal and a first input signal, and that produces a first output signal; and a sub-sampling phase detector that receives the reference signal and a second input signal, and that outputs a second output signal, wherein the first output signal and the second output signal are coupled together.

## Claims

### Claim 1

A circuit for a combined phase detector, comprising:
a tri-state phase frequency detector and charge pump that receives a reference signal and a first input signal, and that produces a first output signal; and
a sub-sampling phase detector that receives the reference signal and a second input signal, and that outputs a second output signal,
wherein the first output signal and the second output signal are coupled together.

### Claim 2 (depends on 1)

The circuit of claim 1, further comprising a loop filter coupled to the first output signal and to the second output signal.

### Claim 3 (depends on 2)

The circuit of claim 2, further comprising a voltage controlled oscillator coupled to the loop filter.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the second input signal is based on an output of the voltage controlled oscillator.

### Claim 5 (depends on 1)

The circuit of claim 1, further comprising a divider that divides the second input signal to provide the first input signal.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the tri-state phase frequency detector and charge pump and the sub-sampling phase detector are configured so that a maximum current of the second output signal is smaller than three times a charge pump current of the tri-state phase frequency detector and charge pump divided by the value of four times the ratio of the frequency of the second input signal and the frequency of the reference signal.

### Claim 7

A circuit for a combined phase detector, comprising:
means for providing a tri-state phase frequency detector and charge pump that receives a reference signal and a first input signal, and that produces a first output signal; and
means for providing a sub-sampling phase detector that receives the reference signal and a second input signal, and that outputs a second output signal,
wherein the first output signal and the second output signal are coupled together.

### Claim 8 (depends on 7)

The circuit of claim 7, further comprising a means for providing a loop filter coupled to the first output signal and to the second output signal.

### Claim 9 (depends on 8)

The circuit of claim 8, further comprising a means for providing voltage controlled oscillator coupled to the loop filter means.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein the second input signal is based on an output of the means for providing a voltage controlled oscillator.

### Claim 11 (depends on 7)

The circuit of claim 7, further comprising a means for providing a divider that divides the second input signal to provide the first input signal.

### Claim 12 (depends on 7)

The circuit of claim 7, wherein the means for providing a tri-state phase frequency detector and charge pump and the means for providing a sub-sampling phase detector are configured so that a maximum current of the second output signal is smaller than three times a charge pump current of the means for providing a tri-state phase frequency detector and charge pump divided by the value of four times the ratio of the frequency of the second input signal and the frequency of the reference signal.

### Claim 13

A method for providing a combined phase detector, comprising:
providing a tri-state phase frequency detector and charge pump that receives a reference signal and a first input signal, and that produces a first output signal; and
providing a sub-sampling phase detector that receives the reference signal and a second input signal, and that outputs a second output signal,
wherein the first output signal and the second output signal are coupled together.

### Claim 14 (depends on 13)

The method of claim 13, further comprising providing a loop filter coupled to the first output signal and to the second output signal.

### Claim 15 (depends on 14)

The method of claim 14, further comprising providing a voltage controlled oscillator coupled to the loop filter.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second input signal is based on an output of the voltage controlled oscillator.

### Claim 17 (depends on 13)

The method of claim 13, further comprising providing a divider that divides the second input signal to provide the first input signal.

### Claim 18 (depends on 13)

The method of claim 13, wherein the tri-state phase frequency detector and charge pump and the sub-sampling phase detector are configured so that a maximum current of the second output signal is smaller than three times a charge pump current of the tri-state phase frequency detector and charge pump divided by the value of four times the ratio of the frequency of the second input signal and the frequency of the reference signal.
