# US 2013/0155801 A1 · Sub word line driver and semiconductor integrated circuit device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0155801 A1 - Document ID: US20130155801A1 - Status: Published application - Kind: A1 - Application number: 13/442,614 - Filed: 2012-04-09 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: Hynix Semiconductor Inc. - Inventors: Tae Sik YUN; Dong Hwee KIM - Web page: https://patentgrep.com/patent/US20130155801A1 ## CPC - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other. ## Claims ### Claim 1 A semiconductor integrated circuit device: a plurality of main word lines; and a plurality of sub word lines configured to be driven in response to a signal of each of the plurality of main word lines, wherein the plurality of sub word lines are extended toward a cell array area from regions of sub word line drivers, respectively disposed at both edges of the cell array area, one sub word line selected from a plurality of sub word lines extended from one region of the sub word line driver of the cell array area and another sub word line adjacent to the selected sub word line are driven in response to signals of different main word lines, respectively, and the signals of the different main word lines have different logic levels. ### Claim 2 (depends on 1) The semiconductor integrated circuit device of claim 1, wherein one sub word line selected from a plurality of sub word lines extended from the other region of the sub word line driver of the cell array area and another sub word line adjacent to the selected sub word line are driven in response to the signals of the different main word lines, respectively. ### Claim 3 (depends on 2) The semiconductor integrated circuit device of claim 2, wherein the plurality of sub word lines are configured so that the sub word lines extended from the one region the sub word line driver and the sub word lines extended from the other region of the sub word line driver are alternately arranged. ### Claim 4 (depends on 3) The semiconductor integrated circuit device of claim 3, wherein an arbitrary sub word line disposed on the cell array area and other sub word lines adjacent to the arbitrary sub word line are driven in response to the signals of the different main word lines, respectively. ### Claim 5 (depends on 4) The semiconductor integrated circuit device of claim 4, wherein the sub word line driver comprises an inverter driven in response to a signal of a selected main word line. ### Claim 6 (depends on 5) The semiconductor integrated circuit device of claim 5, wherein an output signal line of the inverter becomes the sub word line itself without connection to any element. ### Claim 7 (depends on 4) The semiconductor integrated circuit device of claim 4, wherein the plurality of sub word lines arranged on the cell array area are consecutively arranged in the order of a sub word line driven in response to a signal of a first main word line, a sub word line driven in response to a signal of a second main word line, a sub word line driven in response to a signal of a third main word line and a sub word line driven in response to a signal of a fourth main word line. ### Claim 8 (depends on 7) The semiconductor integrated circuit device of claim 7, wherein a keeper transistor for floating prevention is further connected between a pair of adjacent sub word lines extended from the one region of the sub word line driver, and a keeper transistor for floating prevention is further connected between a pair of adjacent sub word lines extended from the other region of the sub word line driver. ### Claim 9 A sub word line driver of a semiconductor integrated circuit device, comprising: a semiconductor substrate configured to comprise an N-well having PMOS transistors formed therein and a P-well having NMOS transistors formed therein; four sub word lines configured to be extended in parallel over the N-well and P-well; first to fourth sub word line selection lines configured to be extended in a direction intersecting with the four sub word lines and formed on the N-well; a pair of VSS lines configured to be formed on the P-well and formed in parallel with the extended direction of the sub word lines; a first main word line configured to comprise a first part having two intersections with one two sub word line of the sub word line selection lines and a second part intersecting with the pair of the VSS lines; and a second main word line configured to comprise a first part having two intersections with an other two sub word line of the sub word line selection lines and a second part intersecting with the pair of the VSS lines. ### Claim 10 (depends on 9) The sub word line driver of claim 9, wherein first and third sub word lines of the four sub word lines are electrically connected to the first main word line, and second and fourth sub word lines of the four sub word lines are electrically connected to the second main word line. ### Claim 11 (depends on 9) The sub word line driver of claim 9, wherein the four sub word lines are arranged in a discontinuous order. ### Claim 12 (depends on 9) The sub word line driver of claim 9, wherein in a main word line of the first and second main word line, positioned at an adjacent part of the N-well and P-well, the first and second parts are connected to each other. ### Claim 13 (depends on 9) The sub word line driver of claim 9, wherein the width of the N-well is at least two times wider than that of the P-well. ### Claim 14 (depends on 9) The sub word line driver of claim 9, wherein one of the pair of the VSS lines is disposed in a space between the first and second sub word lines, and the other of the pair of the VSS lines is disposed in a space between the third and fourth sub word lines. ### Claim 15 A sub word line driver of a semiconductor integrated circuit device, comprising: a semiconductor substrate configured to comprise an N-well having PMOS transistors formed therein and a P-well having NMOS transistors formed therein; four sub word lines configured to be extended in parallel over the N-well and P-well; a sub word line selection line configured to be extended in a direction parallel with the four sub word lines; first and second VSS lines configured to be formed on the P-well, extended in a direction vertical to the extended direction of the sub word lines, and spaced apart from each other at a predetermined interval; a first main word line configured to comprise a pair of bar electrodes substantially intersecting with the four sub word lines and a branch electrode intersecting with the first VSS line; a second main word line configured to comprise a pair of bar electrodes substantially intersecting with the four sub word lines and a branch electrode intersecting with the second VSS line; a third main word line configured to comprise a pair of bar electrodes substantially intersecting with the four sub word lines and a branch electrode intersecting with the first VSS line; and a fourth main word line configured to comprise a pair of bar electrodes substantially intersecting with the four sub word lines and a branch electrode intersecting with the second VSS line, wherein the sub word line driver further comprises a first keeper transistor positioned between the branch electrodes of the first and third main word lines and a second keeper transistor positioned between the branch electrodes of the second and fourth main word lines. ### Claim 16 (depends on 15) The sub word line driver of claim 15, wherein an inverting signal of the sub word line selection line is inputted to gates of the first and second keeper transistors. ### Claim 17 (depends on 15) The sub word line driver of claim 15, wherein the first main word line is electrically related to the first sub word line, the second main word line is electrically related to the second sub word line, the third main word line is electrically related to the third sub word line, and the fourth main word line is electrically related to the fourth sub word line. ### Claim 18 (depends on 15) The sub word line driver of claim 15, wherein the branch electrodes of the first and second main word lines are disposed at an outside of the first sub word line, and the branch electrodes of the third and fourth main word lines are disposed at an outside of the fourth sub word line. ### Claim 19 A semiconductor integrated circuit device, comprising: a first sub word line driver configured to drive a first sub word line in response to a first main word line signal; a second sub word line driver configured to drive a second sub word line adjacent to the first sub word line in response to a second main word line signal; and wherein a logic level of the first main word line signal is different from that of the second main word line signal. ### Claim 20 A semiconductor integrated circuit device, comprising adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.