# US 2013/0155796 A1 · Fabrication and testing method for nonvolatile memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0155796 A1 - Document ID: US20130155796A1 - Status: Published application - Kind: A1 - Application number: 13/711,850 - Filed: 2012-12-12 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Hiroshi Sugawara - Web page: https://patentgrep.com/patent/US20130155796A1 ## CPC - H10P 74/00: Testing or measuring during manufacture or treatment of wafers, substrates or devices - G01R 31/275: {for testing individual semiconductor components within integrated circuits} - G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]} - G11C 29/08: Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing - G11C 29/12005: {comprising voltage or current generators} - G11C 29/26: Accessing multiple arrays (G11C29/24 takes precedence) - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 16/00: Erasable programmable read-only memories (G11C14/00 takes precedence) - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2029/1206: {Location of test circuitry on chip or wafer} - H10W 72/5473: {multiple bond wires connected to a common bond pad} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Provided is a plurality of master chips arranged in a row on the wafer, each master chip including a power supply circuit provides a power supply voltage, and a plurality of slave chips arranged in a column to at least one side of a corresponding master chip among the plurality of master chips, each slave chip including a memory cell array functionally operative in response to the power supply voltage provided by the corresponding master chip during wafer level testing. ## Claims ### Claim 1 A semiconductor wafer, comprising: a plurality of master chips arranged in a row on the wafer, each master chip including at least one master control circuit that provides at least one control signal; and a plurality of slave chips arranged in a column to at least one side of a corresponding master chip among the plurality of master chips, each slave chip including a slave control circuit responsive to the at least one control signal provided by the corresponding master chip during wafer level testing. ### Claim 2 (depends on 1) The semiconductor wafer of claim 1, wherein the plurality of slave chips includes a first plurality of slave chips arranged to one side of the corresponding master chip and a second plurality of slave chips arranged to another side of the corresponding master chip opposite the one side. ### Claim 3 (depends on 1) The semiconductor wafer of claim 1, further comprising: a wiring arrangement extending in a columnar direction and connecting the at least one master control circuit to respective slave control circuits of the plurality of slave chips. ### Claim 4 (depends on 3) The semiconductor wafer of claim 3, wherein the wiring arrangement connects the at least one master control circuit through an uppermost conductive layer of the corresponding master chip, and connects respective slave control circuits of the plurality of slave chips through an uppermost conductive layer of each one of the plurality of slave chips. ### Claim 5 (depends on 4) The semiconductor wafer of claim 4, wherein each one of the plurality of master chips comprises a first connection pad area including a plurality of first connection pads connected to the wiring arrangement, and each one of the plurality of slave chips comprises a second connection pad area including a second plurality of connection pads connected to the wiring arrangement. ### Claim 6 (depends on 1) The semiconductor wafer of claim 1 wherein the at least one master control circuit comprises a power supply circuit, and the at least one control signal comprises at least one power supply voltage. ### Claim 7 A semiconductor wafer, comprising: a plurality of master chips arranged in a row on the wafer, each master chip including a power supply circuit provides a power supply voltage; and a plurality of slave chips arranged in a column to at least one side of a corresponding master chip among the plurality of master chips, each slave chip including a memory cell array functionally operative in response to the power supply voltage provided by the corresponding master chip during wafer level testing. ### Claim 8 (depends on 7) The semiconductor wafer of claim 7, wherein the plurality of slave chips includes a first plurality of slave chips arranged to one side of the corresponding master chip and a second plurality of slave chips arranged to another side of the corresponding master chip opposite the one side. ### Claim 9 (depends on 7) The semiconductor wafer of claim 7, wherein the master chip comprises a master control circuit that provides a control signal, and each slave chip further includes a slave control circuit responsive to the control signal provided by the corresponding master chip during wafer level testing. ### Claim 10 (depends on 9) The semiconductor wafer of claim 9, further comprising: a wiring arrangement extending in a columnar direction and connecting the master control circuit to respective slave control circuits of the plurality of slave chips. ### Claim 11 (depends on 10) The semiconductor wafer of claim 10, wherein the wiring arrangement connects the master control circuit through an uppermost conductive layer of the corresponding master chip, and connects respective slave control circuits of the plurality of slave chips through an uppermost conductive layer of each one of the plurality of slave chips. ### Claim 12 (depends on 11) The semiconductor wafer of claim 11, wherein the corresponding master chip comprises a first connection pad area including a plurality of first connection pads connected to the wiring arrangement, and each slave chip in the plurality of slave chips comprises a second connection pad area including a second plurality of connection pads connected to the wiring arrangement. ### Claim 13 A method of fabricating semiconductor devices, comprising: fabricating a plurality of master chips arranged in a row on a wafer, wherein each master chip includes a master control circuit that provides a control signal; and fabricating a plurality of slave chips arranged in a column to at least one side of a corresponding master chip among the plurality of master chips on the wafer, wherein each slave chip includes a slave control circuit responsive to the control signal provided by the corresponding master chip, wherein the fabricating the plurality of master chips and fabricating the plurality of slave chips is performed by a common set of fabrication processes. ### Claim 14 (depends on 13) The method of claim 13, further comprising: testing the plurality of slave chips on a wafer level by operating the corresponding master control circuit. ### Claim 15 (depends on 14) The method of claim 14, wherein the plurality of slave chips is fabricated to include a first plurality of slave chips arranged to one side of the corresponding master chip and a second plurality of slave chips arranged to another side of the corresponding master chip opposite the one side. ### Claim 16 (depends on 14) The method of claim 14, further comprising: fabricating a wiring arrangement extending in a columnar direction and connecting the master control circuit to respective slave control circuits of the plurality of slave chips. ### Claim 17 (depends on 14) The method of claim 14, wherein the master chip is a power chip and the master control circuit is a power supply circuit, wherein the power chip is used only during wafer level testing of the plurality of slave chips. ### Claim 18 (depends on 17) The method of claim 17, wherein each one of the plurality of slave chips is a nonvolatile memory chip including a memory cell array of nonvolatile memory cells. ### Claim 19 (depends on 17) The method of claim 17, further comprising: identifying bad slave chips among the plurality of slave chips during the wafer level testing and discarding the bad slave chips before packaging. ### Claim 20 (depends on 19) The method of claims 19, further comprising: fabricating a wiring arrangement extending in a columnar direction and connecting the power supply circuit to respective driving circuits of the plurality of slave chips.