# US 2013/0155792 A1 · Semiconductor device having data terminal supplied with plural write data in serial

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0155792 A1
- Document ID: US20130155792A1
- Status: Published application
- Kind: A1
- Application number: 13/715,995
- Filed: 2012-12-14
- Published: 2013-06-20
- Earliest claimed: 2011-12-14
- Assignees: Elpida Memory, Inc.
- Inventors: Yoshinori MATSUI
- Web page: https://patentgrep.com/patent/US20130155792A1

## CPC

- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 7/1066: {Output synchronization}
- G11C 7/1093: {Input synchronization}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C 2207/107: Serial-parallel conversion of data or prefetch
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Disclosed herein is a semiconductor device that includes: a frequency dividing circuit dividing a frequency of a first clock signal to generate second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal; a data input/output terminal; data buses; and a data input/output circuit coupled between the data input/output terminal and the data buses. The data input/output circuit includes a data output circuit and a data input circuit. The data output circuit outputs read data supplied in parallel from the data buses to the data input/output terminal in serial in synchronism with the third clock signal. The data input circuit outputs write data supplied in serial from the data input/output terminal to the data buses in parallel in synchronism with a predetermined one of the second clock signals.

## Claims

### Claim 1

A semiconductor device comprising:
a frequency dividing circuit dividing a frequency of a first clock signal to generate a plurality of second clock signals that are different in phase from one another;
a multiplier circuit multiplying the second clock signals to generate a third clock signal;
a data input/output terminal;
a plurality of data buses; and
a data input/output circuit coupled between the data input/output terminal and the data buses, the data input/output circuit including a data output circuit and a data input circuit, the data output circuit outputting a plurality of read data supplied in parallel from the data buses to the data input/output terminal in serial in synchronism with the third clock signal, and the data input circuit outputting a plurality of write data supplied in serial from the data input/output terminal to the data buses in parallel in synchronism with a predetermined one of the second clock signals.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a data strobe terminal supplied with a data strobe signal,
wherein the data input circuit includes:
a serial-to-parallel conversion circuit converting the write data from serial to parallel in synchronism with the data strobe signal; and
a synchronizing circuit outputting the write data in parallel to the data buses in synchronism with the predetermined one of the second clock signals.

### Claim 3 (depends on 2)

The semiconductor device as claimed in claim 2, wherein
the frequency dividing circuit generates, when a command signal supplied from outside indicates a reading operation, the second clock signals by dividing the frequency of the first clock signal, and
the frequency dividing circuit generates, when the command signal indicates a writing operation, the predetermined one of the second clock signals by dividing the frequency of the first clock signal without generating the other of the second clock signals.

### Claim 4 (depends on 3)

The semiconductor device as claimed in claim 3, wherein the data strobe signal has substantially the same frequency as the third clock signal.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a clock terminal supplied with an external clock signal; and
a clock input circuit that generates the first clock signal based on the external clock signal.

### Claim 6 (depends on 5)

The semiconductor device as claimed in claim 5, wherein
the clock terminal is arranged in a first pad region that extends along a first edge of the semiconductor device, and
the data input/output terminal is arranged in a second pad region that extends along a second edge of the semiconductor device that is different from the first edge.

### Claim 7 (depends on 6)

The semiconductor device as claimed in claim 6, wherein
the frequency dividing circuit is arranged in a first peripheral circuit region that extends along the first pad region, and
the multiplier circuit and the data input/output circuit are arranged in a second peripheral circuit region that extends along the second pad region.

### Claim 8 (depends on 7)

The semiconductor device as claimed in claim 7, further comprising a memory array arranged in a memory cell array region sandwiched between the first and second peripheral circuit regions, the memory array being coupled to the data buses.

### Claim 9 (depends on 5)

The semiconductor device as claimed in claim 5, wherein the first to third clock signals are not phase-controlled with respect to the external clock signal.

### Claim 10

A semiconductor device comprising:
a frequency dividing circuit configured to receive a first clock signal to generate a second clock signal having lower frequency than the first clock signal;
a plurality of data buses;
a data terminal supplied with a plurality of write data in serial;
a data strobe terminal supplied with a data strobe signal;
a serial-to-parallel conversion circuit configured to convert the write data supplied via the data terminal from serial to parallel in synchronism with the data strobe signal; and
a synchronizing circuit configured to output the write data in parallel to the data buses in synchronism with the second clock signal.

### Claim 11 (depends on 10)

The semiconductor device as claimed in claim 10, wherein
the data buses have a n-bit width,
the serial-to-parallel conversion circuit is configured to convert n-bit write data from serial to parallel in synchronism with the data strobe signal, and
the synchronizing circuit is configured to output the n-bit write data in parallel to the n-bit data buses in synchronism with the second clock signal.

### Claim 12 (depends on 10)

The semiconductor device as claimed in claim 10, wherein
the frequency dividing circuit is configured to generate the second clock signal by dividing a frequency of the first clock signal during a writing operation; and
the frequency dividing circuit is configured to generate a plurality of second clock signals that are different in phase from one another by dividing the frequency of the first clock signal during a reading operation.

### Claim 13 (depends on 12)

The semiconductor device as claimed in claim 12, further comprising:
a multiplier circuit configured to multiply the plurality of second clock signals to generate a third clock signal; and
a data output circuit configured to output a plurality of read data supplied in parallel from the data buses to the data terminal in serial in synchronism with the third clock signal.

### Claim 14

A semiconductor device comprising:
a memory cell array including a plurality of memory cells;
a plurality of data buses receiving, in a data read mode, parallel-read-data from the memory cell array and supplying, in a data write mode, parallel-write-date to the memory cell array;
a first clock circuit including a plurality of output nodes and configured to generate, in the data read mode, a plurality of first clock signals at the output nodes, respectively, and to generate, in the data write mode, at least one second clock signal at an associated one of the output nodes while stopping generation of clock signal or signals at remaining one or ones of the output nodes;
a second clock circuit coupled to the output nodes of the first clock circuit and configured to produce, in the data read mode, a third clock signal in response to the first clock signals and, in the data write mode, a fourth clock signal in response to the second clock signal, the third clock signal being greater in frequency than the fourth clock signal;
a data terminal;
a date output circuit coupled to the data buses to convert the parallel-read-data into serial-read-data in response to the third clock signal, the data output circuit being coupled to the data terminal to drive the data terminal in response to the serial-read-data; and
a data input circuit coupled to the data terminal to convert serial-write data into the parallel-write-data, the data output circuit coupled to the data buses to supply the parallel-write data to the data buses in response to the fourth clock signal.

### Claim 15 (depends on 14)

The device as claimed in claim 14, further comprising a data strobe terminal receiving, in the data write mode, a data strobe signal, the data input circuit converting the serial-write data into the parallel-write-data in response to the data strobe signal.

### Claim 16 (depends on 14)

The device as claimed in claim 14, wherein the memory cell array is formed between the first and second clock circuits.

### Claim 17 (depends on 16)

The device as claimed in claim 16, wherein each of the second clock circuit and the data input and output circuits is formed between the memory cell and the data terminal.

### Claim 18 (depends on 17)

The device as claimed in claim 17, wherein the output nodes of the first clock circuit are coupled to the second clock circuit through a plurality of interconnection lines, the interconnection lines passing over the memory cell array.

### Claim 19 (depends on 14)

The device as claimed in claim 14, wherein the first clock circuit maintains, in the data write mode, the remaining one or ones of the output nodes at a substantially constant level.